diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2021-03-23 08:54:18 +0800 |
|---|---|---|
| committer | Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> | 2021-04-27 10:42:04 +0000 |
| commit | a2ebfa91ef55a18f5da02f50576392fd37fa3798 (patch) | |
| tree | eb8b81f789ec5406a24d4ca0895a472fc0344e25 /Documentation/devicetree | |
| parent | 3cca777427f6a48d74fd26d6159612befdb95385 (diff) | |
MLK-25349-1 dt-bindings: imx6q-pcie: add one regulator used to power up pcie phy
Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
(cherry picked from commit c14681471c737280d93d1e5f83221576caf352ee)
(cherry picked from commit dc80c759ebb82f5ffc8e7ae263427b3b9d49d854)
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index d208fe06df11..8a4edaf2cee1 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -51,6 +51,9 @@ Optional properties: The regulator will be enabled when initializing the PCIe host and disabled either as part of the init process or when shutting down the host. +- vph-supply: Should specify the regulator in charge of VPH one of the three + PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage + supplies. Might be used to distinguish different HW board designs. - ext_osc: use the external oscillator as ref clock( 1: external OSC is used, 0 internal PLL is used). - hard_wired: the PCIe port is hard wired to the EP device(0: one slot |