ARM: tegra: Add PWM definition to Tegra DFLL binding

Added definition of PWM PMIC integration to Tegra DFLL binding.

Bug 1442709

Change-Id: I262978d8d9ae9edb37dd433a9d7bfcc95d393b79
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/360128
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

1 files changed, 78 insertions, 9 deletions

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt
index 202a2ff22955..c7e216565d56 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt
@@ -2,9 +2,9 @@ NVIDIA Tegra DFLL clock source data in the SoC DTS file:
 
 Required properties:
 - compatible : Must be one of the following
-	"nvidia,tegra124-dfll".
-	"nvidia,tegra148-dfll".
-	"nvidia,tegra114-dfll",
+	"nvidia,tegra124-dfll"
+	"nvidia,tegra148-dfll"
+	"nvidia,tegra114-dfll"
 - reg : Must contain the starting physical address and length for the DFLL's
   MMIO register space including the DFLL-to-I2C controller interface and the
   DFLL's I2C controller.
@@ -30,13 +30,15 @@ NVIDIA Tegra DFLL clock source data in the board DTS file
 Required properties:
 - board-params : phandle pointing to the board-specific configuration data
   for this DFLL instance.
+
+Optional properties:
 - i2c-pmic-integration : phandle pointing to the integration data for
   PMIC controlled by this DFLL instance via I2C interface.
-Note that after future addition of device tree support for PMIC controlled via
-PWM interface, this property become optional and mutually exclusive with
-pwm-pmic-integration.
+- pwm-pmic-integration : phandle pointing to the integration data for
+  PMIC controlled by this DFLL instance via PWM interface.
+Note that one and only one of 'i2c-pmic-integration', or 'pwm-pmic-integration',
+must be specified.
 
-Optional properties:
 - i2c-quiet-output-workaround : If the DFLL IP block version implemented on
   this SoC requires the I2C output to the PMIC to be quiesced before disabling
   it, this property should be set.
@@ -74,8 +76,8 @@ Optional properties:
 - cg-scale : if present, divide loop gain by 8 (see 'cg' above).
 
 - fixed-output-forcing : force PMIC voltage during req change for a fixed time.
-- auto-output-forcing : force PMIC voltage during req change for a dynamic time.
-- no-output-forcing : don't force PMIC voltage output during request change.
+- auto-output-forcing  : force PMIC voltage during req change for a dynamic time.
+- no-output-forcing    : don't force PMIC voltage output during request change.
 Note that one and only one of 'fixed-output-forcing', or 'auto-output-forcing',
 or 'no-output-forcing' must be specified.
 
@@ -123,3 +125,70 @@ cpu_dfll_pmic_integration {
         sel-conversion-slope = <1>;
         pmic-undershoot-gb = <100>;
 };
+
+DFLL PWM PMIC integration node in the board DTS file
+
+Required properties:
+- compatible : Must be
+	"nvidia,tegra124-dfll-pwm"
+- pwm-data-gpio : DFLL PWM data GPIO.
+
+- #pwm-cells : Number of cells in PWM regulator specification, must be 2.
+- pwm-regulator : phandle pointing to the node of regulator controlled by DFLL.
+  PWM regulator properties are defined by pwm-regulator.txt binding; pwm-list
+  of the regulator node must refer to PWM PMIC integration node, and include 2
+  cells in the spec: cell 0 for PWM channel number within DFLL, and cell 1 for
+  PWM period in nanoseconds.
+
+Optional properties:
+- pwm-1wire-buffer : DFLL is connected to PMIC by 1 wire (data only) via external
+  buffer with tri-state control.
+- pwm-1wire-direct : DFLL is directly connected to PMIC by 1 wire (data only).
+- pwm-2wire        : DFLL is directly connected to PMIC by 2 wires (data/clock).
+Note that one and only one of 'pwm-1wire-buffer', or 'pwm-1wire-direct',
+or 'pwm-2wire' must be specified.
+
+- pwm-buffer-ctrl-gpio : External buffer control GPIO.
+  Must be specified if 'pwm-1wire-buffer' property is present.
+- pwm-clk-gpio : DFLL PWM clock GPIO.
+  Must be specified if 'pwm-2wire' property is present.
+- pwm-delta-mode : Stop PWM clock when no changes.
+  Can be specified if 'pwm-2wire' property is present.
+
+Example:
+
+pwm_dfll: cpu_dfll_pmic_integration {
+	compatible = "nvidia,tegra124-dfll-pwm";
+	pwm-1wire-buffer;
+	pwm-data-gpio = <&gpio TEGRA_GPIO(X, 0) 0>;
+	pwm-buffer-ctrl-gpio = <&gpio TEGRA_GPIO(S, 5) 1>;
+	#pwm-cells = <2>;
+	pwm-regulator = <&cpu_pwm_reg>;
+};
+
+pwm_regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+	cpu_pwm_reg: pwm-regulator@0 {
+		reg = <0>;
+		compatible = "regulator-pwm";
+		pwms = <&pwm_dfll 0 2500>;
+		regulator-name = "vdd-cpu-pwm-reg";
+		regulator-min-microvolt = <675000>;
+		regulator-max-microvolt = <1275000>;
+		regulator-init-microvolt = <1000000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-n-voltages = <33>;
+		voltage-time-sel = <80>;
+		idle-gpio = <&gpio TEGRA_GPIO(X, 2) 0>;
+
+		consumers {
+			c1 {
+				regulator-consumer-supply = "vdd_cpu";
+			};
+		};
+	};
+};