diff options
| author | Liu Ying <victor.liu@nxp.com> | 2017-07-03 13:07:23 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 907a88e19b8f5d9762d7b5b106c3d2ee50fb1090 (patch) | |
| tree | e35f56e27f9afd4e6a43a7c49d8312e220d64a53 /Documentation/devicetree | |
| parent | c242e43f8874501d861bfa34810ddd9a6fd4beb6 (diff) | |
MLK-15110-3 gpu: imx: Add i.MX8 DPR(Display Prefetch Resolve) support
The Display Prefetch Resolve(DPR) is a processor of fetching display data
before the display pipeline which needs data to drive pixels in the active
display region. The data is transformed, or resolved from a variety of
tiled buffer formats into linear format. The DPR transaction sequences are
issued with a high level of DRAM efficiency. This patch adds the base
driver support for i.MX8qm/qxp DPR.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index da728cc81af4..9365b54c7c29 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -214,6 +214,38 @@ prg@56040000 { power-domains = <&pd_dc0>; }; +Freescale i.MX8 DPRC (Display Prefetch Resolve Channel) +======================================================= +Required properties: +- compatible: should be "fsl,<chip>-dpr-channel" +- reg: should be register base and length as documented in the + datasheet +- fsl,sc-resource: SCU resource number as described in + Documentation/devicetree/bindings/soc/fsl/imx_rsrc.txt +- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one + is the primary PRG and the second one(if available) is the auxiliary PRG + which is used to fetch luma chunk of a YUV frame with 2 planars. +- clocks: phandles to the DPRC apb, b and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt, + Documentation/devicetree/bindings/clock/imx8qm-clock.txt and + Documentation/devicetree/bindings/clock/imx8qxp-clock.txt +- clock-names: should be "apb", "b" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +dpr-channel@56100000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56100000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_VIDEO0>; + fsl,prgs = <&prg4>, <&prg5>; + clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>, + <&clk IMX8QM_DC0_DPR1_B_CLK>, + <&clk IMX8QM_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; +}; + Parallel display support ======================== |