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| author | Liu Ying <victor.liu@nxp.com> | 2017-06-19 11:39:56 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | b33d51329cb4a2eccf131858ff13d120896b6dda (patch) | |
| tree | d3a2e9e4978060f6c56a90e6001dc3648516d69d /Documentation/devicetree | |
| parent | 4358277f999d6edee93077acb63fd7409bbbb487 (diff) | |
MLK-15110-15 gpu: imx: dpu: fetchdecode: Add DPR support
This patch adds DPR support for fetchdecode in the DPU base driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index 9365b54c7c29..de3616775fa1 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -74,6 +74,8 @@ Required properties: Documentation/devicetree/bindings/clock/imx8qm-clock.txt, and in Documentation/devicetree/bindings/clock/imx8qxp-clock.txt. - power-domains: phandle pointing to power domain. +- fsl,dpr-channels: phandles to the DPR channels attached to this DPU, + sorted by memory map addresses. Only valid for i.MX8qm and i.MX8qxp. Optional properties: - port@[0-1]: Port nodes with endpoint definitions as defined in Documentation/devicetree/bindings/media/video-interfaces.txt. @@ -110,6 +112,9 @@ dpu: dpu@56180000 { <&clk IMX8QM_DC0_DISP1_CLK>; clock-names = "pll0", "pll1", "disp0", "disp1"; power-domains = <&pd_dc0>; + fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, + <&dpr1_channel3>, <&dpr2_channel1>, + <&dpr2_channel2>, <&dpr2_channel3>; dpu1_disp1: port@1 { reg = <1>; |