diff options
| author | Matt LaPlante <kernel1@cyberdogtech.com> | 2009-04-27 15:06:31 +0200 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2009-06-12 18:01:47 +0200 |
| commit | 19f594600110377ec4037fdf7fb93a25ec516212 (patch) | |
| tree | bf88707b65f0138b754d896300976e474098a50d /Documentation/scsi/ncr53c8xx.txt | |
| parent | 19af5cdb7c79ff5ec96a99893ffb7f894f4a3dc1 (diff) | |
trivial: Miscellaneous documentation typo fixes
Fix various typos in documentation txts.
Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'Documentation/scsi/ncr53c8xx.txt')
| -rw-r--r-- | Documentation/scsi/ncr53c8xx.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/scsi/ncr53c8xx.txt b/Documentation/scsi/ncr53c8xx.txt index 230e30846ef2..08e2b4d04aab 100644 --- a/Documentation/scsi/ncr53c8xx.txt +++ b/Documentation/scsi/ncr53c8xx.txt @@ -206,7 +206,7 @@ of MOVE MEMORY instructions. The 896 and the 895A allows handling of the phase mismatch context from SCRIPTS (avoids the phase mismatch interrupt that stops the SCSI processor until the C code has saved the context of the transfer). -Implementing this without using LOAD/STORE instructions would be painfull +Implementing this without using LOAD/STORE instructions would be painful and I didn't even want to try it. The 896 chip supports 64 bit PCI transactions and addressing, while the @@ -240,7 +240,7 @@ characteristics. This feature may also reduce average command latency. In order to really gain advantage of this feature, devices must have a reasonable cache size (No miracle is to be expected for a low-end hard disk with 128 KB or less). -Some kown SCSI devices do not properly support tagged command queuing. +Some known SCSI devices do not properly support tagged command queuing. Generally, firmware revisions that fix this kind of problems are available at respective vendor web/ftp sites. All I can say is that the hard disks I use on my machines behave well with |