ENGR00275023-4 ARM: imx: Setting CPU isolation according to dts

Different boards may use different PMICs, and the PMICs' power
rail ramp up time can impact the DSM mode a lot, so we need to
adjust the CPU isolation timing setting according to board dts
setting, if there is no such setting defined in dts, use default
value.

Signed-off-by: Anson Huang <b20788@freescale.com>

1 files changed, 20 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/imx/gpc.txt b/Documentation/devicetree/bindings/arm/imx/gpc.txt
new file mode 100644
index 000000000000..5a363a85822c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/imx/gpc.txt
@@ -0,0 +1,20 @@
+Freescale imx GPC bindings
+
+Optional properties:
+- fsl,cpu_pupscr_sw2iso: for powering up CPU, number of 32K clock cycle PGC will wait before negating isolation signal.
+- fsl,cpu_pupscr_sw: for powering up CPU, number of 32K clock cycle PGC will wait before asserting isolation signal.
+- fsl,cpu_pdnscr_iso2sw: for powering down CPU, number of ipg clock cycle PGC will wait before negating isolation signal.
+- fsl,cpu_pdnscr_iso: for powering down CPU, number of ipg clock cycle PGC will wait before asserting isolation signal.
+
+These properties are for adjusting the GPC PGC CPU power up/down setting, if there is no such property in dts, then default
+value in GPC PGC registers will be used.
+
+
+Example:
+
+	&gpc {
+		fsl,cpu_pupscr_sw2iso = <0xf>;
+		fsl,cpu_pupscr_sw = <0xf>;
+		fsl,cpu_pdnscr_iso2sw = <0x1>;
+		fsl,cpu_pdnscr_iso = <0x1>;
+	};