diff options
| author | Leif Lindholm <leif.lindholm@arm.com> | 2010-07-14 14:23:54 +0100 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2010-11-04 09:53:04 -0800 |
| commit | 2f32db5cbea15c9094208e53793f0bdff1585620 (patch) | |
| tree | a786b281e4a4ce3b970238b1e14543a01aa4f61b /Documentation | |
| parent | 9ab8a403297057ad72054563da39825c8a7d3ad7 (diff) | |
ARM: Add SWP/SWPB emulation for ARMv7 processors (v5)
The SWP instruction was deprecated in the ARMv6 architecture, superseded
by the LDREX/STREX family of instructions for
load-linked/store-conditional operations. The ARMv7 multiprocessing
extensions mandate that SWP/SWPB instructions are treated as undefined
from reset, with the ability to enable them through the System Control
Register SW bit.
This patch adds the alternative solution to emulate the SWP and SWPB
instructions using LDREX/STREX sequences, and log statistics to
/proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also
modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when
user RO.
Signed-off-by: Leif Lindholm <leif.lindholm@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Change-Id: I10616601fb05643561e5301064c115ee268846bf
(cherry picked from commit 81b437e0fabd3049f141bc5820970c325c478574)
Reviewed-on: http://git-master/r/10091
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/arm/00-INDEX | 2 | ||||
| -rw-r--r-- | Documentation/arm/swp_emulation | 27 |
2 files changed, 29 insertions, 0 deletions
diff --git a/Documentation/arm/00-INDEX b/Documentation/arm/00-INDEX index 82e418d648d0..05e13a9f32aa 100644 --- a/Documentation/arm/00-INDEX +++ b/Documentation/arm/00-INDEX @@ -30,3 +30,5 @@ memory.txt - description of the virtual memory layout nwfpe/ - NWFPE floating point emulator documentation +swp_emulation + - SWP/SWPB emulation handler/logging description diff --git a/Documentation/arm/swp_emulation b/Documentation/arm/swp_emulation new file mode 100644 index 000000000000..af903d22fd93 --- /dev/null +++ b/Documentation/arm/swp_emulation @@ -0,0 +1,27 @@ +Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE) +--------------------------------------------------------------------- + +ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds +moving to the load-locked/store-conditional instructions LDREX and STREX. + +ARMv7 multiprocessing extensions introduce the ability to disable these +instructions, triggering an undefined instruction exception when executed. +Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB +sequence. If a memory access fault (an abort) occurs, a segmentation fault is +signalled to the triggering process. + +/proc/cpu/swp_emulation holds some statistics/information, including the PID of +the last process to trigger the emulation to be invocated. For example: +--- +Emulated SWP: 12 +Emulated SWPB: 0 +Aborted SWP{B}: 1 +Last process: 314 +--- + +NOTE: when accessing uncached shared regions, LDREX/STREX rely on an external +transaction monitoring block called a global monitor to maintain update +atomicity. If your system does not implement a global monitor, this option can +cause programs that perform SWP operations to uncached memory to deadlock, as +the STREX operation will always fail. + |