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authorBjorn Helgaas <bhelgaas@google.com>2016-03-15 08:55:52 -0500
committerBjorn Helgaas <bhelgaas@google.com>2016-03-15 08:55:52 -0500
commit562df5c8521e1371f3cbd0b7b868034da376d714 (patch)
tree798a5b2f688a60307889c632a20e32aae65d51fa /Documentation
parentc334f9c89e40d2c9f4598e87e186bf3264d39e51 (diff)
parent5a3aa2a8fae4ce1a3ad786d212b8fffca8ee72f5 (diff)
Merge branch 'pci/host-designware' into next
* pci/host-designware: PCI: designware: Add driver for prototyping kits based on ARC SDP PCI: designware: Add default link up check if sub-driver doesn't override PCI: designware: Add generic dw_pcie_wait_for_link() ARC: Add PCI support
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/pci/designware-pcie.txt17
1 files changed, 17 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 5b0853df9d5a..64f2fff12128 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -28,3 +28,20 @@ Optional properties:
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+
+Example configuration:
+
+ pcie: pcie@0xdffff000 {
+ compatible = "snps,dw-pcie";
+ reg = <0xdffff000 0x1000>, /* Controller registers */
+ <0xd0000000 0x2000>; /* PCI config space */
+ reg-names = "ctrlreg", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
+ 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
+ interrupts = <25>, <24>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ };