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author | Peter Chen <peter.chen@freescale.com> | 2015-02-04 16:20:33 +0800 |
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committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-23 16:42:48 +0300 |
commit | 7cc10fe915491ec1548cb03317ffdb9e2b534824 (patch) | |
tree | 3dcfbf193404d341ccee3dcdae6152c65451f07d /Documentation | |
parent | 44f06b3afdca9e3da846b0db62b14fa7b6bb0cde (diff) |
MLK-10202-2 doc: usb: mxs-phy: add tx-d-cal property
Add tx-d-cal property
Signed-off-by: Peter Chen <peter.chen@freescale.com>
(cherry picked from commit ebb97b3d3ca99516d3daac09813ae480de2adffe)
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/phy/mxs-usb-phy.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt index 1d25b04cd05e..5d6303014470 100644 --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt @@ -21,6 +21,9 @@ Optional properties: that terminates the DP output signal. Default: 45 - fsl,tx-d-cal: Integer [79-119]. Current trimming value (as a percentage) of the 17.78mA TX reference current. Default: 100 +- tx-d-cal: Try to adjust this value to improve signal quality, and pass + USB Certification, the value is from 0x0 to 0xf, and the register offset + is 0x10 (USBPHY_TX). Example: usbphy1: usbphy@020c9000 { @@ -28,4 +31,5 @@ usbphy1: usbphy@020c9000 { reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; fsl,anatop = <&anatop>; + tx-d-cal = <0x5>; }; |