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authorLinus Torvalds <torvalds@linux-foundation.org>2021-09-01 15:25:28 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2021-09-01 15:25:28 -0700
commit866147b8fa59530812fc769027a94468d89401e7 (patch)
tree1d97cf66b7db6765570ba824c51bd3dc84b561fc /Documentation
parent634135a07b887a8ad8904da8c147407650747a38 (diff)
parent06779631d18ff2901af604eadea0d7b2193db7a1 (diff)
Merge tag 'drivers-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann: "These are updates for drivers that are tied to a particular SoC, including the correspondig device tree bindings: - A couple of reset controller changes for unisoc, uniphier, renesas and zte platforms - memory controller driver fixes for omap and tegra - Rockchip io domain driver updates - Lots of updates for qualcomm platforms, mostly touching their firmware and power management drivers - Tegra FUSE and firmware driver updateѕ - Support for virtio transports in the SCMI firmware framework - cleanup of ixp4xx drivers, towards enabling multiplatform support and bringing it up to date with modern platforms - Minor updates for keystone, mediatek, omap, renesas" * tag 'drivers-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (96 commits) reset: simple: remove ZTE details in Kconfig help soc: rockchip: io-domain: Remove unneeded semicolon soc: rockchip: io-domain: add rk3568 support dt-bindings: power: add rk3568-pmu-io-domain support bus: ixp4xx: return on error in ixp4xx_exp_probe() soc: renesas: Prefer memcpy() over strcpy() firmware: tegra: Stop using seq_get_buf() soc/tegra: fuse: Enable fuse clock on suspend for Tegra124 soc/tegra: fuse: Add runtime PM support soc/tegra: fuse: Clear fuse->clk on driver probe failure soc/tegra: pmc: Prevent racing with cpuilde driver soc/tegra: bpmp: Remove unused including <linux/version.h> dt-bindings: soc: ti: pruss: Add dma-coherent property soc: ti: Remove pm_runtime_irq_safe() usage for smartreflex soc: ti: pruss: Enable support for ICSSG subsystems on K3 AM64x SoCs dt-bindings: soc: ti: pruss: Update bindings for K3 AM64x SoCs firmware: arm_scmi: Use WARN_ON() to check configured transports firmware: arm_scmi: Fix boolconv.cocci warnings soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing soc: mediatek: mmsys: add MT8365 support ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml61
-rw-r--r--Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml168
-rw-r--r--Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt1
-rw-r--r--Documentation/devicetree/bindings/firmware/arm,scmi.yaml8
-rw-r--r--Documentation/devicetree/bindings/power/qcom,rpmpd.yaml1
-rw-r--r--Documentation/devicetree/bindings/power/rockchip-io-domain.txt135
-rw-r--r--Documentation/devicetree/bindings/power/rockchip-io-domain.yaml360
-rw-r--r--Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml5
-rw-r--r--Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml4
-rw-r--r--Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml65
-rw-r--r--Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml88
-rw-r--r--Documentation/devicetree/bindings/reset/uniphier-reset.txt61
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt87
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml114
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml3
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml1
-rw-r--r--Documentation/devicetree/bindings/soc/rockchip/grf.yaml19
-rw-r--r--Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml41
18 files changed, 919 insertions, 303 deletions
diff --git a/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml b/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml
new file mode 100644
index 000000000000..52e18600ecff
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel IXP4xx CompactFlash Card Controller
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ The IXP4xx network processors have a CompactFlash interface that presents
+ a CompactFlash card to the system as a true IDE (parallel ATA) device. The
+ device is always connected to the expansion bus of the IXP4xx SoCs using one
+ or two chip select areas and address translating logic on the board. The
+ node must be placed inside a chip select node on the IXP4xx expansion bus.
+
+properties:
+ compatible:
+ const: intel,ixp4xx-compact-flash
+
+ reg:
+ items:
+ - description: Command interface registers
+ - description: Control interface registers
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+allOf:
+ - $ref: pata-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ bus@c4000000 {
+ compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
+ reg = <0xc4000000 0x1000>;
+ native-endian;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
+ dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
+ ide@1,0 {
+ compatible = "intel,ixp4xx-compact-flash";
+ reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <12 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
new file mode 100644
index 000000000000..5fb4e7bfa4da
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel IXP4xx Expansion Bus Controller
+
+description: |
+ The IXP4xx expansion bus controller handles access to devices on the
+ memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
+ including IXP42x, IXP43x, IXP45x and IXP46x.
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+properties:
+ $nodename:
+ pattern: '^bus@[0-9a-f]+$'
+
+ compatible:
+ items:
+ - enum:
+ - intel,ixp42x-expansion-bus-controller
+ - intel,ixp43x-expansion-bus-controller
+ - intel,ixp45x-expansion-bus-controller
+ - intel,ixp46x-expansion-bus-controller
+ - const: syscon
+
+ reg:
+ description: Control registers for the expansion bus, these are not
+ inside the memory range handled by the expansion bus.
+ maxItems: 1
+
+ native-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: The IXP4xx has a peculiar MMIO access scheme, as it changes
+ the access pattern for words (swizzling) on the bus depending on whether
+ the SoC is running in big-endian or little-endian mode. Thus the
+ registers must always be accessed using native endianness.
+
+ "#address-cells":
+ description: |
+ The first cell is the chip select number.
+ The second cell is the address offset within the bank.
+ const: 2
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+ dma-ranges: true
+
+patternProperties:
+ "^.*@[0-7],[0-9a-f]+$":
+ description: Devices attached to chip selects are represented as
+ subnodes.
+ type: object
+
+ properties:
+ intel,ixp4xx-eb-t1:
+ description: Address timing, extend address phase with n cycles.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 3
+
+ intel,ixp4xx-eb-t2:
+ description: Setup chip select timing, extend setup phase with n cycles.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 3
+
+ intel,ixp4xx-eb-t3:
+ description: Strobe timing, extend strobe phase with n cycles.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+
+ intel,ixp4xx-eb-t4:
+ description: Hold timing, extend hold phase with n cycles.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 3
+
+ intel,ixp4xx-eb-t5:
+ description: Recovery timing, extend recovery phase with n cycles.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 15
+
+ intel,ixp4xx-eb-cycle-type:
+ description: The type of cycles to use on the expansion bus for this
+ chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ intel,ixp4xx-eb-byte-access-on-halfword:
+ description: Allow byte read access on half word devices.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+ intel,ixp4xx-eb-hpi-hrdy-pol-high:
+ description: Set HPI HRDY polarity to active high when using HPI.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+ intel,ixp4xx-eb-mux-address-and-data:
+ description: Multiplex address and data on the data bus.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+ intel,ixp4xx-eb-ahb-split-transfers:
+ description: Enable AHB split transfers.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+ intel,ixp4xx-eb-write-enable:
+ description: Enable write cycles.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+ intel,ixp4xx-eb-byte-access:
+ description: Expansion bus uses only 8 bits. The default is to use
+ 16 bits.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+required:
+ - compatible
+ - reg
+ - native-endian
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - dma-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ bus@50000000 {
+ compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
+ reg = <0xc4000000 0x28>;
+ native-endian;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x01000000>,
+ <1 0x0 0x51000000 0x01000000>;
+ dma-ranges = <0 0x0 0x50000000 0x01000000>,
+ <1 0x0 0x51000000 0x01000000>;
+ flash@0,0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ reg = <0 0x00000000 0x1000000>;
+ intel,ixp4xx-eb-t3 = <3>;
+ intel,ixp4xx-eb-cycle-type = <0>;
+ intel,ixp4xx-eb-byte-access-on-halfword = <1>;
+ intel,ixp4xx-eb-write-enable = <1>;
+ intel,ixp4xx-eb-byte-access = <0>;
+ };
+ serial@1,0 {
+ compatible = "exar,xr16l2551", "ns8250";
+ reg = <1 0x00000000 0x10>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <1843200>;
+ intel,ixp4xx-eb-t3 = <3>;
+ intel,ixp4xx-eb-cycle-type = <1>;
+ intel,ixp4xx-eb-write-enable = <1>;
+ intel,ixp4xx-eb-byte-access = <1>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index c9e97409e853..12c316ff4834 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -9,6 +9,7 @@ Required properties:
"fsl,imx53-sdma"
"fsl,imx6q-sdma"
"fsl,imx7d-sdma"
+ "fsl,imx6ul-sdma"
"fsl,imx8mq-sdma"
"fsl,imx8mm-sdma"
"fsl,imx8mn-sdma"
diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
index cebf6ffe70d5..5c4c6782e052 100644
--- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
@@ -34,6 +34,10 @@ properties:
- description: SCMI compliant firmware with ARM SMC/HVC transport
items:
- const: arm,scmi-smc
+ - description: SCMI compliant firmware with SCMI Virtio transport.
+ The virtio transport only supports a single device.
+ items:
+ - const: arm,scmi-virtio
interrupts:
description:
@@ -172,6 +176,7 @@ patternProperties:
Each sub-node represents a protocol supported. If the platform
supports a dedicated communication channel for a particular protocol,
then the corresponding transport properties must be present.
+ The virtio transport does not support a dedicated communication channel.
properties:
reg:
@@ -195,7 +200,6 @@ patternProperties:
required:
- compatible
- - shmem
if:
properties:
@@ -209,6 +213,7 @@ then:
required:
- mboxes
+ - shmem
else:
if:
@@ -219,6 +224,7 @@ else:
then:
required:
- arm,smc-id
+ - shmem
examples:
- |
diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
index 4807b560f00d..239f37881cae 100644
--- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
@@ -30,6 +30,7 @@ properties:
- qcom,sc8180x-rpmhpd
- qcom,sdm845-rpmhpd
- qcom,sdx55-rpmhpd
+ - qcom,sm6115-rpmpd
- qcom,sm8150-rpmhpd
- qcom,sm8250-rpmhpd
- qcom,sm8350-rpmhpd
diff --git a/Documentation/devicetree/bindings/power/rockchip-io-domain.txt b/Documentation/devicetree/bindings/power/rockchip-io-domain.txt
deleted file mode 100644
index e66fd4eab71c..000000000000
--- a/Documentation/devicetree/bindings/power/rockchip-io-domain.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-Rockchip SRAM for IO Voltage Domains:
--------------------------------------
-
-IO domain voltages on some Rockchip SoCs are variable but need to be
-kept in sync between the regulators and the SoC using a special
-register.
-
-A specific example using rk3288:
-- If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
- bit 7 of GRF_IO_VSEL needs to be 0. If the regulator hooked up to
- that same pin is 1.8V then bit 7 of GRF_IO_VSEL needs to be 1.
-
-Said another way, this driver simply handles keeping bits in the SoC's
-general register file (GRF) in sync with the actual value of a voltage
-hooked up to the pins.
-
-Note that this driver specifically doesn't include:
-- any logic for deciding what voltage we should set regulators to
-- any logic for deciding whether regulators (or internal SoC blocks)
- should have power or not have power
-
-If there were some other software that had the smarts of making
-decisions about regulators, it would work in conjunction with this
-driver. When that other software adjusted a regulator's voltage then
-this driver would handle telling the SoC about it. A good example is
-vqmmc for SD. In that case the dw_mmc driver simply is told about a
-regulator. It changes the regulator between 3.3V and 1.8V at the
-right time. This driver notices the change and makes sure that the
-SoC is on the same page.
-
-
-Required properties:
-- compatible: should be one of:
- - "rockchip,px30-io-voltage-domain" for px30
- - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
- - "rockchip,rk3188-io-voltage-domain" for rk3188
- - "rockchip,rk3228-io-voltage-domain" for rk3228
- - "rockchip,rk3288-io-voltage-domain" for rk3288
- - "rockchip,rk3328-io-voltage-domain" for rk3328
- - "rockchip,rk3368-io-voltage-domain" for rk3368
- - "rockchip,rk3368-pmu-io-voltage-domain" for rk3368 pmu-domains
- - "rockchip,rk3399-io-voltage-domain" for rk3399
- - "rockchip,rk3399-pmu-io-voltage-domain" for rk3399 pmu-domains
- - "rockchip,rv1108-io-voltage-domain" for rv1108
- - "rockchip,rv1108-pmu-io-voltage-domain" for rv1108 pmu-domains
-
-Deprecated properties:
-- rockchip,grf: phandle to the syscon managing the "general register files"
- Systems should move the io-domains to a sub-node of the grf simple-mfd.
-
-You specify supplies using the standard regulator bindings by including
-a phandle the relevant regulator. All specified supplies must be able
-to report their voltage. The IO Voltage Domain for any non-specified
-supplies will be not be touched.
-
-Possible supplies for PX30:
-- vccio6-supply: The supply connected to VCCIO6.
-- vccio1-supply: The supply connected to VCCIO1.
-- vccio2-supply: The supply connected to VCCIO2.
-- vccio3-supply: The supply connected to VCCIO3.
-- vccio4-supply: The supply connected to VCCIO4.
-- vccio5-supply: The supply connected to VCCIO5.
-- vccio-oscgpi-supply: The supply connected to VCCIO_OSCGPI.
-
-Possible supplies for PX30 pmu-domains:
-- pmuio1-supply: The supply connected to PMUIO1.
-- pmuio2-supply: The supply connected to PMUIO2.
-
-Possible supplies for rk3188:
-- ap0-supply: The supply connected to AP0_VCC.
-- ap1-supply: The supply connected to AP1_VCC.
-- cif-supply: The supply connected to CIF_VCC.
-- flash-supply: The supply connected to FLASH_VCC.
-- lcdc0-supply: The supply connected to LCD0_VCC.
-- lcdc1-supply: The supply connected to LCD1_VCC.
-- vccio0-supply: The supply connected to VCCIO0.
-- vccio1-supply: The supply connected to VCCIO1.
- Sometimes also labeled VCCIO1 and VCCIO2.
-
-Possible supplies for rk3228:
-- vccio1-supply: The supply connected to VCCIO1.
-- vccio2-supply: The supply connected to VCCIO2.
-- vccio3-supply: The supply connected to VCCIO3.
-- vccio4-supply: The supply connected to VCCIO4.
-
-Possible supplies for rk3288:
-- audio-supply: The supply connected to APIO4_VDD.
-- bb-supply: The supply connected to APIO5_VDD.
-- dvp-supply: The supply connected to DVPIO_VDD.
-- flash0-supply: The supply connected to FLASH0_VDD. Typically for eMMC
-- flash1-supply: The supply connected to FLASH1_VDD. Also known as SDIO1.
-- gpio30-supply: The supply connected to APIO1_VDD.
-- gpio1830 The supply connected to APIO2_VDD.
-- lcdc-supply: The supply connected to LCDC_VDD.
-- sdcard-supply: The supply connected to SDMMC0_VDD.
-- wifi-supply: The supply connected to APIO3_VDD. Also known as SDIO0.
-
-Possible supplies for rk3368:
-- audio-supply: The supply connected to APIO3_VDD.
-- dvp-supply: The supply connected to DVPIO_VDD.
-- flash0-supply: The supply connected to FLASH0_VDD. Typically for eMMC
-- gpio30-supply: The supply connected to APIO1_VDD.
-- gpio1830 The supply connected to APIO4_VDD.
-- sdcard-supply: The supply connected to SDMMC0_VDD.
-- wifi-supply: The supply connected to APIO2_VDD. Also known as SDIO0.
-
-Possible supplies for rk3368 pmu-domains:
-- pmu-supply: The supply connected to PMUIO_VDD.
-- vop-supply: The supply connected to LCDC_VDD.
-
-Possible supplies for rk3399:
-- bt656-supply: The supply connected to APIO2_VDD.
-- audio-supply: The supply connected to APIO5_VDD.
-- sdmmc-supply: The supply connected to SDMMC0_VDD.
-- gpio1830 The supply connected to APIO4_VDD.
-
-Possible supplies for rk3399 pmu-domains:
-- pmu1830-supply:The supply connected to PMUIO2_VDD.
-
-Example:
-
- io-domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
- rockchip,grf = <&grf>;
-
- audio-supply = <&vcc18_codec>;
- bb-supply = <&vcc33_io>;
- dvp-supply = <&vcc_18>;
- flash0-supply = <&vcc18_flashio>;
- gpio1830-supply = <&vcc33_io>;
- gpio30-supply = <&vcc33_pmuio>;
- lcdc-supply = <&vcc33_lcd>;
- sdcard-supply = <&vccio_sd>;
- wifi-supply = <&vcc18_wl>;
- };
diff --git a/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml b/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
new file mode 100644
index 000000000000..1727bf108979
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
@@ -0,0 +1,360 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SRAM for IO Voltage Domains
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ IO domain voltages on some Rockchip SoCs are variable but need to be
+ kept in sync between the regulators and the SoC using a special
+ register.
+
+ A specific example using rk3288
+ If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
+ bit 7 of GRF_IO_VSEL needs to be 0. If the regulator hooked up to
+ that same pin is 1.8V then bit 7 of GRF_IO_VSEL needs to be 1.
+
+ Said another way, this driver simply handles keeping bits in the SoCs
+ General Register File (GRF) in sync with the actual value of a voltage
+ hooked up to the pins.
+
+ Note that this driver specifically does not include
+ any logic for deciding what voltage we should set regulators to
+ any logic for deciding whether regulators (or internal SoC blocks)
+ should have power or not have power
+
+ If there were some other software that had the smarts of making
+ decisions about regulators, it would work in conjunction with this
+ driver. When that other software adjusted a regulators voltage then
+ this driver would handle telling the SoC about it. A good example is
+ vqmmc for SD. In that case the dw_mmc driver simply is told about a
+ regulator. It changes the regulator between 3.3V and 1.8V at the
+ right time. This driver notices the change and makes sure that the
+ SoC is on the same page.
+
+ You specify supplies using the standard regulator bindings by including
+ a phandle the relevant regulator. All specified supplies must be able
+ to report their voltage. The IO Voltage Domain for any non-specified
+ supplies will be not be touched.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,px30-io-voltage-domain
+ - rockchip,px30-pmu-io-voltage-domain
+ - rockchip,rk3188-io-voltage-domain
+ - rockchip,rk3228-io-voltage-domain
+ - rockchip,rk3288-io-voltage-domain
+ - rockchip,rk3328-io-voltage-domain
+ - rockchip,rk3368-io-voltage-domain
+ - rockchip,rk3368-pmu-io-voltage-domain
+ - rockchip,rk3399-io-voltage-domain
+ - rockchip,rk3399-pmu-io-voltage-domain
+ - rockchip,rk3568-pmu-io-voltage-domain
+ - rockchip,rv1108-io-voltage-domain
+ - rockchip,rv1108-pmu-io-voltage-domain
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+allOf:
+ - $ref: "#/$defs/px30"
+ - $ref: "#/$defs/px30-pmu"
+ - $ref: "#/$defs/rk3188"
+ - $ref: "#/$defs/rk3228"
+ - $ref: "#/$defs/rk3288"
+ - $ref: "#/$defs/rk3328"
+ - $ref: "#/$defs/rk3368"
+ - $ref: "#/$defs/rk3368-pmu"
+ - $ref: "#/$defs/rk3399"
+ - $ref: "#/$defs/rk3399-pmu"
+ - $ref: "#/$defs/rk3568-pmu"
+ - $ref: "#/$defs/rv1108"
+ - $ref: "#/$defs/rv1108-pmu"
+
+$defs:
+ px30:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,px30-io-voltage-domain
+
+ then:
+ properties:
+ vccio1-supply:
+ description: The supply connected to VCCIO1.
+ vccio2-supply:
+ description: The supply connected to VCCIO2.
+ vccio3-supply:
+ description: The supply connected to VCCIO3.
+ vccio4-supply:
+ description: The supply connected to VCCIO4.
+ vccio5-supply:
+ description: The supply connected to VCCIO5.
+ vccio6-supply:
+ description: The supply connected to VCCIO6.
+ vccio-oscgpi-supply:
+ description: The supply connected to VCCIO_OSCGPI.
+
+ px30-pmu:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,px30-pmu-io-voltage-domain
+
+ then:
+ properties:
+ pmuio1-supply:
+ description: The supply connected to PMUIO1.
+ pmuio2-supply:
+ description: The supply connected to PMUIO2.
+
+ rk3188:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3188-io-voltage-domain
+
+ then:
+ properties:
+ ap0-supply:
+ description: The supply connected to AP0_VCC.
+ ap1-supply:
+ description: The supply connected to AP1_VCC.
+ cif-supply:
+ description: The supply connected to CIF_VCC.
+ flash-supply:
+ description: The supply connected to FLASH_VCC.
+ lcdc0-supply:
+ description: The supply connected to LCD0_VCC.
+ lcdc1-supply:
+ description: The supply connected to LCD1_VCC.
+ vccio0-supply:
+ description: The supply connected to VCCIO0.
+ vccio1-supply:
+ description: The supply connected to VCCIO1. Also labeled as VCCIO2.
+
+ rk3228:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3228-io-voltage-domain
+
+ then:
+ properties:
+ vccio1-supply:
+ description: The supply connected to VCCIO1.
+ vccio2-supply:
+ description: The supply connected to VCCIO2.
+ vccio3-supply:
+ description: The supply connected to VCCIO3.
+ vccio4-supply:
+ description: The supply connected to VCCIO4.
+
+ rk3288:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3288-io-voltage-domain
+
+ then:
+ properties:
+ audio-supply:
+ description: The supply connected to APIO4_VDD.
+ bb-supply:
+ description: The supply connected to APIO5_VDD.
+ dvp-supply:
+ description: The supply connected to DVPIO_VDD.
+ flash0-supply:
+ description: The supply connected to FLASH0_VDD. Typically for eMMC.
+ flash1-supply:
+ description: The supply connected to FLASH1_VDD. Also known as SDIO1.
+ gpio30-supply:
+ description: The supply connected to APIO1_VDD.
+ gpio1830-supply:
+ description: The supply connected to APIO2_VDD.
+ lcdc-supply:
+ description: The supply connected to LCDC_VDD.
+ sdcard-supply:
+ description: The supply connected to SDMMC0_VDD.
+ wifi-supply:
+ description: The supply connected to APIO3_VDD. Also known as SDIO0.
+
+ rk3328:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3328-io-voltage-domain
+
+ then:
+ properties:
+ vccio1-supply:
+ description: The supply connected to VCCIO1.
+ vccio2-supply:
+ description: The supply connected to VCCIO2.
+ vccio3-supply:
+ description: The supply connected to VCCIO3.
+ vccio4-supply:
+ description: The supply connected to VCCIO4.
+ vccio5-supply:
+ description: The supply connected to VCCIO5.
+ vccio6-supply:
+ description: The supply connected to VCCIO6.
+ pmuio-supply:
+ description: The supply connected to VCCIO_PMU.
+
+ rk3368:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3368-io-voltage-domain
+
+ then:
+ properties:
+ audio-supply:
+ description: The supply connected to APIO3_VDD.
+ dvp-supply:
+ description: The supply connected to DVPIO_VDD.
+ flash0-supply:
+ description: The supply connected to FLASH0_VDD. Typically for eMMC.
+ gpio30-supply:
+ description: The supply connected to APIO1_VDD.
+ gpio1830-supply:
+ description: The supply connected to APIO4_VDD.
+ sdcard-supply:
+ description: The supply connected to SDMMC0_VDD.
+ wifi-supply:
+ description: The supply connected to APIO2_VDD. Also known as SDIO0.
+
+ rk3368-pmu:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3368-pmu-io-voltage-domain
+
+ then:
+ properties:
+ pmu-supply:
+ description: The supply connected to PMUIO_VDD.
+ vop-supply:
+ description: The supply connected to LCDC_VDD.
+
+ rk3399:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3399-io-voltage-domain
+
+ then:
+ properties:
+ audio-supply:
+ description: The supply connected to APIO5_VDD.
+ bt656-supply:
+ description: The supply connected to APIO2_VDD.
+ gpio1830-supply:
+ description: The supply connected to APIO4_VDD.
+ sdmmc-supply:
+ description: The supply connected to SDMMC0_VDD.
+
+ rk3399-pmu:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3399-pmu-io-voltage-domain
+
+ then:
+ properties:
+ pmu1830-supply:
+ description: The supply connected to PMUIO2_VDD.
+
+ rk3568-pmu:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3568-pmu-io-voltage-domain
+
+ then:
+ properties:
+ pmuio1-supply:
+ description: The supply connected to PMUIO1.
+ pmuio2-supply:
+ description: The supply connected to PMUIO2.
+ vccio1-supply:
+ description: The supply connected to VCCIO1.
+ vccio2-supply:
+ description: The supply connected to VCCIO2.
+ vccio3-supply:
+ description: The supply connected to VCCIO3.
+ vccio4-supply:
+ description: The supply connected to VCCIO4.
+ vccio5-supply:
+ description: The supply connected to VCCIO5.
+ vccio6-supply:
+ description: The supply connected to VCCIO6.
+ vccio7-supply:
+ description: The supply connected to VCCIO7.
+
+ rv1108:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rv1108-io-voltage-domain
+
+ then:
+ properties:
+ vccio1-supply:
+ description: The supply connected to APIO1_VDD.
+ vccio2-supply:
+ description: The supply connected to APIO2_VDD.
+ vccio3-supply:
+ description: The supply connected to APIO3_VDD.
+ vccio5-supply:
+ description: The supply connected to APIO5_VDD.
+ vccio6-supply:
+ description: The supply connected to APIO6_VDD.
+
+ rv1108-pmu:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rv1108-pmu-io-voltage-domain
+
+ then:
+ properties:
+ pmu-supply:
+ description: The supply connected to PMUIO_VDD.
+
+examples:
+ - |
+ io-domains {
+ compatible = "rockchip,rk3288-io-voltage-domain";
+ audio-supply = <&vcc18_codec>;
+ bb-supply = <&vcc33_io>;
+ dvp-supply = <&vcc_18>;
+ flash0-supply = <&vcc18_flashio>;
+ gpio1830-supply = <&vcc33_io>;
+ gpio30-supply = <&vcc33_pmuio>;
+ lcdc-supply = <&vcc33_lcd>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vcc18_wl>;
+ };
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
index e2d85a1e1d63..a054757f4d9f 100644
--- a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
@@ -21,6 +21,11 @@ properties:
- const: "qcom,sc7180-aoss-cc"
- const: "qcom,sdm845-aoss-cc"
+ - description: on SC7280 SoCs the following compatibles must be specified
+ items:
+ - const: "qcom,sc7280-aoss-cc"
+ - const: "qcom,sdm845-aoss-cc"
+
- description: on SDM845 SoCs the following compatibles must be specified
items:
- const: "qcom,sdm845-aoss-cc"
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
index d7d8cec9419f..831ea8d5d83f 100644
--- a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
+++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
@@ -21,6 +21,10 @@ properties:
- const: "qcom,sc7180-pdc-global"
- const: "qcom,sdm845-pdc-global"
+ - description: on SC7280 SoCs the following compatibles must be specified
+ items:
+ - const: "qcom,sc7280-pdc-global"
+
- description: on SDM845 SoCs the following compatibles must be specified
items:
- const: "qcom,sdm845-pdc-global"
diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
new file mode 100644
index 000000000000..b13514e6783d
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L USBPHY Control
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description:
+ The RZ/G2L USBPHY Control mainly controls reset and power down of the
+ USB/PHY.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
+ - const: renesas,rzg2l-usbphy-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+ description: |
+ The phandle's argument in the reset specifier is the PHY reset associated
+ with the USB port.
+ 0 = Port 1 Phy reset
+ 1 = Port 2 Phy reset
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - power-domains
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0x11c40000 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml b/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml
new file mode 100644
index 000000000000..29e4a900cad7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier peripheral core reset in glue layer
+
+description: |
+ Some peripheral core reset belongs to its own glue layer. Before using
+ this core reset, it is necessary to control the clocks and resets to
+ enable this layer. These clocks and resets should be described in each
+ property.
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+properties:
+ compatible:
+ enum:
+ - socionext,uniphier-pro4-usb3-reset
+ - socionext,uniphier-pro5-usb3-reset
+ - socionext,uniphier-pxs2-usb3-reset
+ - socionext,uniphier-ld20-usb3-reset
+ - socionext,uniphier-pxs3-usb3-reset
+ - socionext,uniphier-pro4-ahci-reset
+ - socionext,uniphier-pxs2-ahci-reset
+ - socionext,uniphier-pxs3-ahci-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ oneOf:
+ - items: # for Pro4, Pro5
+ - const: gio
+ - const: link
+ - items: # for others
+ - const: link
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ oneOf:
+ - items: # for Pro4, Pro5
+ - const: gio
+ - const: link
+ - items: # for others
+ - const: link
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+examples:
+ - |
+ usb-glue@65b00000 {
+ compatible = "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65b00000 0x400>;
+
+ usb_rst: reset@0 {
+ compatible = "socionext,uniphier-ld20-usb3-reset";
+ reg = <0x0 0x4>;
+ #reset-cells = <1>;
+ clock-names = "link";
+ clocks = <&sys_clk 14>;
+ reset-names = "link";
+ resets = <&sys_rst 14>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt
deleted file mode 100644
index 88e06e5e8d23..000000000000
--- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-UniPhier glue reset controller
-
-
-Peripheral core reset in glue layer
------------------------------------
-
-Some peripheral core reset belongs to its own glue layer. Before using
-this core reset, it is necessary to control the clocks and resets to enable
-this layer. These clocks and resets should be described in each property.
-
-Required properties:
-- compatible: Should be
- "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
- "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
- "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
- "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
- "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
- "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
- "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
- "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
-- #reset-cells: Should be 1.
-- reg: Specifies offset and length of the register set for the device.
-- clocks: A list of phandles to the clock gate for the glue layer.
- According to the clock-names, appropriate clocks are required.
-- clock-names: Should contain
- "gio", "link" - for Pro4 and Pro5 SoCs
- "link" - for others
-- resets: A list of phandles to the reset control for the glue layer.
- According to the reset-names, appropriate resets are required.
-- reset-names: Should contain
- "gio", "link" - for Pro4 and Pro5 SoCs
- "link" - for others
-
-Example:
-
- usb-glue@65b00000 {
- compatible = "socionext,uniphier-ld20-dwc3-glue",
- "simple-mfd";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x65b00000 0x400>;
-
- usb_rst: reset@0 {
- compatible = "socionext,uniphier-ld20-usb3-reset";
- reg = <0x0 0x4>;
- #reset-cells = <1>;
- clock-names = "link";
- clocks = <&sys_clk 14>;
- reset-names = "link";
- resets = <&sys_rst 14>;
- };
-
- regulator {
- ...
- };
-
- phy {
- ...
- };
- ...
- };
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
deleted file mode 100644
index 783dc81b0f26..000000000000
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
+++ /dev/null
@@ -1,87 +0,0 @@
-Qualcomm Always-On Subsystem side channel binding
-
-This binding describes the hardware component responsible for side channel
-requests to the always-on subsystem (AOSS), used for certain power management
-requests that is not handled by the standard RPMh interface. Each client in the
-SoC has it's own block of message RAM and IRQ for communication with the AOSS.
-The protocol used to communicate in the message RAM is known as Qualcomm
-Messaging Protocol (QMP)
-
-The AOSS side channel exposes control over a set of resources, used to control
-a set of debug related clocks and to affect the low power state of resources
-related to the secondary subsystems. These resources are exposed as a set of
-power-domains.
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be one of:
- "qcom,sc7180-aoss-qmp"
- "qcom,sc7280-aoss-qmp"
- "qcom,sdm845-aoss-qmp"
- "qcom,sm8150-aoss-qmp"
- "qcom,sm8250-aoss-qmp"
- "qcom,sm8350-aoss-qmp"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: the base address and size of the message RAM for this
- client's communication with the AOSS
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: should specify the AOSS message IRQ for this client
-
-- mboxes:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: reference to the mailbox representing the outgoing doorbell
- in APCS for this client, as described in mailbox/mailbox.txt
-
-- #clock-cells:
- Usage: optional
- Value type: <u32>
- Definition: must be 0
- The single clock represents the QDSS clock.
-
-- #power-domain-cells:
- Usage: optional
- Value type: <u32>
- Definition: must be 1
- The provided power-domains are:
- CDSP state (0), LPASS state (1), modem state (2), SLPI
- state (3), SPSS state (4) and Venus state (5).
-
-= SUBNODES
-The AOSS side channel also provides the controls for three cooling devices,
-these are expressed as subnodes of the QMP node. The name of the node is used
-to identify the resource and must therefor be "cx", "mx" or "ebi".
-
-- #cooling-cells:
- Usage: optional
- Value type: <u32>
- Definition: must be 2
-
-= EXAMPLE
-
-The following example represents the AOSS side-channel message RAM and the
-mechanism exposing the power-domains, as found in SDM845.
-
- aoss_qmp: qmp@c300000 {
- compatible = "qcom,sdm845-aoss-qmp";
- reg = <0x0c300000 0x100000>;
- interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
- mboxes = <&apss_shared 0>;
-
- #power-domain-cells = <1>;
-
- cx_cdev: cx {
- #cooling-cells = <2>;
- };
-
- mx_cdev: mx {
- #cooling-cells = <2>;
- };
- };
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
new file mode 100644
index 000000000000..93e4b737ee1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Always-On Subsystem side channel binding
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+ This binding describes the hardware component responsible for side channel
+ requests to the always-on subsystem (AOSS), used for certain power management
+ requests that is not handled by the standard RPMh interface. Each client in the
+ SoC has it's own block of message RAM and IRQ for communication with the AOSS.
+ The protocol used to communicate in the message RAM is known as Qualcomm
+ Messaging Protocol (QMP)
+
+ The AOSS side channel exposes control over a set of resources, used to control
+ a set of debug related clocks and to affect the low power state of resources
+ related to the secondary subsystems. These resources are exposed as a set of
+ power-domains.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sc7180-aoss-qmp
+ - qcom,sc7280-aoss-qmp
+ - qcom,sc8180x-aoss-qmp
+ - qcom,sdm845-aoss-qmp
+ - qcom,sm8150-aoss-qmp
+ - qcom,sm8250-aoss-qmp
+ - qcom,sm8350-aoss-qmp
+ - const: qcom,aoss-qmp
+
+ reg:
+ maxItems: 1
+ description:
+ The base address and size of the message RAM for this client's
+ communication with the AOSS
+
+ interrupts:
+ maxItems: 1
+ description:
+ Should specify the AOSS message IRQ for this client
+
+ mboxes:
+ maxItems: 1
+ description:
+ Reference to the mailbox representing the outgoing doorbell in APCS for
+ this client, as described in mailbox/mailbox.txt
+
+ "#clock-cells":
+ const: 0
+ description:
+ The single clock represents the QDSS clock.
+
+ "#power-domain-cells":
+ const: 1
+ description: |
+ The provided power-domains are:
+ CDSP state (0), LPASS state (1), modem state (2), SLPI
+ state (3), SPSS state (4) and Venus state (5).
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - mboxes
+ - "#clock-cells"
+
+additionalProperties: false
+
+patternProperties:
+ "^(cx|mx|ebi)$":
+ type: object
+ description:
+ The AOSS side channel also provides the controls for three cooling devices,
+ these are expressed as subnodes of the QMP node. The name of the node is
+ used to identify the resource and must therefor be "cx", "mx" or "ebi".
+
+ properties:
+ "#cooling-cells":
+ const: 2
+
+ required:
+ - "#cooling-cells"
+
+ additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ aoss_qmp: qmp@c300000 {
+ compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0x0c300000 0x100000>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apss_shared 0>;
+
+ #clock-cells = <0>;
+ #power-domain-cells = <1>;
+
+ cx_cdev: cx {
+ #cooling-cells = <2>;
+ };
+
+ mx_cdev: mx {
+ #cooling-cells = <2>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
index 4663c2bcad50..a776cd37c297 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
@@ -51,6 +51,9 @@ properties:
interconnect-names:
const: qup-core
+ iommus:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
index d511f01fcac6..cc3fe5ed7421 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
@@ -39,6 +39,7 @@ properties:
- qcom,rpm-msm8996
- qcom,rpm-msm8998
- qcom,rpm-sdm660
+ - qcom,rpm-sm6115
- qcom,rpm-sm6125
- qcom,rpm-qcs404
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 62fa72cfea34..dfebf425ca49 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -15,7 +15,6 @@ properties:
- items:
- enum:
- rockchip,rk3288-sgrf
- - rockchip,rv1108-pmugrf
- rockchip,rv1108-usbgrf
- const: syscon
- items:
@@ -41,6 +40,7 @@ properties:
- rockchip,rk3568-grf
- rockchip,rk3568-pmugrf
- rockchip,rv1108-grf
+ - rockchip,rv1108-pmugrf
- const: syscon
- const: simple-mfd
@@ -198,21 +198,28 @@ allOf:
compatible:
contains:
enum:
- - rockchip,px30-pmugrf
- rockchip,px30-grf
+ - rockchip,px30-pmugrf
+ - rockchip,rk3188-grf
- rockchip,rk3228-grf
- rockchip,rk3288-grf
- rockchip,rk3328-grf
- - rockchip,rk3368-pmugrf
- rockchip,rk3368-grf
- - rockchip,rk3399-pmugrf
+ - rockchip,rk3368-pmugrf
- rockchip,rk3399-grf
+ - rockchip,rk3399-pmugrf
+ - rockchip,rk3568-pmugrf
+ - rockchip,rv1108-grf
+ - rockchip,rv1108-pmugrf
then:
properties:
io-domains:
- description:
- Documentation/devicetree/bindings/power/rockchip-io-domain.txt
+ type: object
+
+ $ref: "/schemas/power/rockchip-io-domain.yaml#"
+
+ unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
index 9790617af1bc..9d128b9e7deb 100644
--- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
+++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
@@ -68,6 +68,7 @@ properties:
- ti,k2g-pruss # for 66AK2G SoC family
- ti,am654-icssg # for K3 AM65x SoC family
- ti,j721e-icssg # for K3 J721E SoC family
+ - ti,am642-icssg # for K3 AM64x SoC family
reg:
maxItems: 1
@@ -84,6 +85,8 @@ properties:
dma-ranges:
maxItems: 1
+ dma-coherent: true
+
power-domains:
description: |
This property is as per sci-pm-domain.txt.
@@ -231,8 +234,8 @@ patternProperties:
description: |
Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
- AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x & J721E SoCs ). IEP
- is used for creating PTP clocks and generating PPS signals.
+ AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x, J721E & AM64x SoCs).
+ IEP is used for creating PTP clocks and generating PPS signals.
type: object
@@ -323,17 +326,29 @@ additionalProperties: false
# - interrupt-controller
# - pru
-if:
- properties:
- compatible:
- contains:
- enum:
- - ti,k2g-pruss
- - ti,am654-icssg
- - ti,j721e-icssg
-then:
- required:
- - power-domains
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,k2g-pruss
+ - ti,am654-icssg
+ - ti,j721e-icssg
+ - ti,am642-icssg
+ then:
+ required:
+ - power-domains
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,k2g-pruss
+ then:
+ required:
+ - dma-coherent
examples:
- |