Merge branch 'display/next' into next

* display/next: (578 commits)
  LF-4828 media: epdc: add video mode for panel ED060XH7U2_VB3300
  LF-4819-3 media: epdc: add runtime pm support for epdc
  LF-5015-2 drm/panel: Add Rocktech Himax8394f MIPI DSI panel support
  LF-5015-1 dt-bindings: display: Add Rocktech Himax8394f TFT LCD panel bindings
  LF-4887-6 drm/imx: lcdif: Add MPU interface(8080 mode) support
  ...

14 files changed, 761 insertions, 17 deletions

diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml
index d3dd7a79b909..9c9b991fc366 100644
--- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml
@@ -45,6 +45,26 @@ properties:
       - const: cec
       - const: packet
 
+  adi,dsi-channel:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Only for ADV7533 and ADV7535. DSI channel number to be used
+      when communicating with the DSI peripheral.
+      It should be one of 0, 1, 2 or 3.
+
+  adi,addr-cec:
+    description:
+      Only for ADV7533 and ADV7535. The I2C DSI-CEC register map
+      address to be programmed into the MAIN register map.
+  adi,addr-edid:
+    description:
+      Only for ADV7533 and ADV7535. The I2C EDID register map
+      to be programmed into the MAIN register map.
+  adi,addr-pkt:
+    description:
+      Only for ADV7533 and ADV7535. The I2C PACKET register map
+      to be programmed into the MAIN register map.
+ 
   clocks:
     description: Reference to the CEC clock.
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/bridge/it6263.txt b/Documentation/devicetree/bindings/display/bridge/it6263.txt
new file mode 100644
index 000000000000..dc032dbdc6b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/it6263.txt
@@ -0,0 +1,27 @@
+ITE IT6263 LVDS to HDMI bridge bindings
+
+Required properties:
+	- compatible: "ite,it6263"
+	- reg: i2c address of the bridge
+	- video input: this subnode can contain a video input port node
+	  to connect the bridge to a LVDS output interface (See this
+	  documentation [1]).
+
+Optional properties:
+	- split-mode: boolean. if this exists, split mode is enabled,
+	  otherwise, single mode is enabled.
+	- reset-gpios: OF device-tree gpio specification for SYSRSTN pin.
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+
+		port {
+			it6263_0_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
index 350fb8f400f0..3a7318d84b60 100644
--- a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
@@ -19,7 +19,9 @@ allOf:
 
 properties:
   compatible:
-    const: fsl,imx8mq-nwl-dsi
+    enum:
+      - fsl,imx8mq-nwl-dsi
+      - fsl,imx8ulp-nwl-dsi
 
   reg:
     maxItems: 1
@@ -44,6 +46,7 @@ properties:
       - description: TX_ESC clock (used in escape mode)
       - description: PHY_REF clock
       - description: LCDIF clock
+      - description: PHY_PARENT clock (optional)
 
   clock-names:
     items:
@@ -52,6 +55,7 @@ properties:
       - const: tx_esc
       - const: phy_ref
       - const: lcdif
+      - const: phy_parent
 
   mux-controls:
     description:
diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt b/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt
new file mode 100644
index 000000000000..9021e6ad9299
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt
@@ -0,0 +1,40 @@
+Legacy Freescale RA169Z20 adapter card for Seiko 43WVFIG panel, driver bindings
+
+This is an adapter card made for the 4.3", 800x480, LCD panel Seiko 43WVFIG.
+The LCD panel is a 24bit DPI bus, while the adapter card has two ports:
+18-bit and 24-bit data input. For the 18-bit data input, the adapter card
+is demuxing some of the data lines, in order to feed all of the 24 lines
+needed by the LCD.
+
+Required properties:
+- compatible: 	"nxp,seiko-43wvfig"
+- bus_mode:	must be one of <18> or <24>, depending on the input port
+		used (18-bit or 24-bit)
+- port:		input and output port nodes with endpoint definitions as
+		defined in Documentation/devicetree/bindings/graph.txt;
+		the input port should be connected to an lcd controller
+		while the output port should be connected to the Seiko
+		43wvfig LCD panel
+
+Example:
+	seiko_adapter: seiko-adapter {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,seiko-43wvfig";
+		bus_mode = <18>;
+
+		port@0 {
+			reg = <0>;
+			adapter_in: endpoint {
+				remote-endpoint = <&lcdif_out>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			adapter_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+
+-
diff --git a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt
new file mode 100644
index 000000000000..fd4246136d37
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt
@@ -0,0 +1,60 @@
+Samsung MIPI DSIM bridge bindings
+
+The MIPI DSIM host controller drives the video signals from
+display controller to video peripherals using DSI protocol.
+This is an un-managed DSI bridge. In order to use this bridge,
+an encoder or bridge must be implemented to manage the platform
+specific initializations.
+
+Required properties:
+- compatible: 		"fsl,imx8mm-mipi-dsim"
+- reg: 			the register range of the MIPI DSIM controller
+- interrupts: 		the interrupt number for this module
+- clock, clock-names: 	phandles to the MIPI-DSI clocks described in
+  Documentation/devicetree/bindings/clock/clock-bindings.txt
+	"cfg"		- DSIM access clock
+	"pll-ref"	- DSIM PHY PLL reference clock
+- assigned-clocks:	phandles to clocks that requires initial configuration
+- assigned-clock-rates:	rates of the clocks that requires initial configuration
+- pref-clk:		Assign DPHY PLL reference clock frequency. If not exists,
+			DSIM bridge driver will use the default lock frequency
+			which is 27MHz.
+- port: 		input and output port nodes with endpoint definitions as
+			defined in Documentation/devicetree/bindings/graph.txt;
+			the input port should be connected to an encoder or a
+			bridge that manages this MIPI DSIM host and the output
+			port should be connected to a panel or a bridge input
+			port
+
+Optional properties:
+-dsi-gpr:		a phandle which provides the MIPI DSIM control and gpr registers
+
+example:
+	mipi_dsi: mipi_dsi@32E10000 {
+		compatible = "fsl,imx8mm-mipi-dsim";
+		reg = <0x0 0x32e10000 0x0 0x400>;
+		clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>,
+			 <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>;
+		clock-names = "cfg", "pll-ref";
+		assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>,
+				  <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>;
+		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+					 <&clk IMX8MM_VIDEO_PLL1_OUT>;
+		assigned-clock-rates = <266000000>, <594000000>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		dsi-gpr = <&dispmix_gpr>;
+		status = "disabled";
+
+		port@0 {
+			dsim_from_lcdif: endpoint {
+				remote-endpoint = <&lcdif_to_dsim>;
+			};
+		};
+
+		port@1 {
+			dsim_to_adv7535: endpoint {
+				remote-endpoint = <&adv7535_from_dsim>;
+			};
+		};
+
+	};
diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
index 900a56cae80e..22bf7e6afbcf 100644
--- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
+++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
@@ -55,6 +55,12 @@ properties:
     $ref: /schemas/graph.yaml#/properties/port
     description: The LCDIF output port
 
+  max-memory-bandwidth:
+    - description: |
+	maximum bandwidth in bytes per second that the
+	controller can handle; if not present, the memory
+	interface is fast enough to handle all possible video modes
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
index 3c35338a2867..524b1871a0a3 100644
--- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
@@ -110,6 +110,289 @@ prg@21cc000 {
 	fsl,pres = <&pre1>, <&pre2>, <&pre3>;
 };
 
+Freescale i.MX DPU
+====================
+
+Required properties:
+- compatible: Should be "fsl,<chip>-dpu"
+- reg: should be register base and length as documented in the
+  datasheet
+- interrupt-parent: phandle pointing to the parent interrupt controller.
+- interrupts, interrupt-names: Should contain interrupts and names as
+  documented in the datasheet.
+- clocks, clock-names: phandles to the DPU clocks described in
+  Documentation/devicetree/bindings/clock/clock-bindings.txt
+  The following clocks are expected on i.MX8qxp:
+           "pll0" - PLL clock for display interface 0
+           "pll1" - PLL clock for display interface 1
+           "disp0" - pixel clock for display interface 0
+           "disp1" - pixel clock for display interface 1
+  The needed clock numbers for each are documented in
+  Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
+- power-domains: phandles pointing to power domain.
+- power-domain-names: power domain names relevant to power-domains phandles.
+- fsl,dpr-channels: phandles to the DPR channels attached to this DPU,
+  sorted by memory map addresses.
+- fsl,pixel-combiner: phandle to the pixel combiner unit attached to this DPU.
+Optional properties:
+- port@[0-1]: Port nodes with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+  ports 0 and 1 should correspond to display interface 0 and
+  display interface 1, respectively.
+
+example:
+
+dpu: dpu@56180000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,imx8qxp-dpu";
+	reg = <0x56180000 0x40000>;
+	interrupt-parent = <&irqsteer_dpu>;
+	interrupts = <448>, <449>, <450>,  <64>,
+		      <65>,  <66>,  <67>,  <68>,
+		      <69>,  <70>, <193>, <194>,
+		     <195>, <196>, <197>,  <72>,
+		      <73>,  <74>,  <75>,  <76>,
+		      <77>,  <78>,  <79>,  <80>,
+		      <81>, <199>, <200>, <201>,
+		     <202>, <203>, <204>, <205>,
+		     <206>, <207>, <208>,   <0>,
+		       <1>,   <2>,   <3>,   <4>,
+		      <82>,  <83>,  <84>,  <85>,
+		     <209>, <210>, <211>, <212>;
+	interrupt-names = "store9_shdload",
+			  "store9_framecomplete",
+			  "store9_seqcomplete",
+			  "extdst0_shdload",
+			  "extdst0_framecomplete",
+			  "extdst0_seqcomplete",
+			  "extdst4_shdload",
+			  "extdst4_framecomplete",
+			  "extdst4_seqcomplete",
+			  "extdst1_shdload",
+			  "extdst1_framecomplete",
+			  "extdst1_seqcomplete",
+			  "extdst5_shdload",
+			  "extdst5_framecomplete",
+			  "extdst5_seqcomplete",
+			  "disengcfg_shdload0",
+			  "disengcfg_framecomplete0",
+			  "disengcfg_seqcomplete0",
+			  "framegen0_int0",
+			  "framegen0_int1",
+			  "framegen0_int2",
+			  "framegen0_int3",
+			  "sig0_shdload",
+			  "sig0_valid",
+			  "sig0_error",
+			  "disengcfg_shdload1",
+			  "disengcfg_framecomplete1",
+			  "disengcfg_seqcomplete1",
+			  "framegen1_int0",
+			  "framegen1_int1",
+			  "framegen1_int2",
+			  "framegen1_int3",
+			  "sig1_shdload",
+			  "sig1_valid",
+			  "sig1_error",
+			  "cmdseq_error",
+			  "comctrl_sw0",
+			  "comctrl_sw1",
+			  "comctrl_sw2",
+			  "comctrl_sw3",
+			  "framegen0_primsync_on",
+			  "framegen0_primsync_off",
+			  "framegen0_secsync_on",
+			  "framegen0_secsync_off",
+			  "framegen1_primsync_on",
+			  "framegen1_primsync_off",
+			  "framegen1_secsync_on",
+			  "framegen1_secsync_off";
+	clocks = <&dc_lpcg IMX_DC0_PLL0_CLK>,
+		 <&dc_lpcg IMX_DC0_PLL1_CLK>,
+		 <&dc_lpcg IMX_DC0_DISP0_CLK>,
+		 <&dc_lpcg IMX_DC0_DISP1_CLK>;
+	clock-names = "pll0", "pll1", "disp0", "disp1";
+	power-domains = <&pd IMX_SC_R_DC_0>,
+			<&pd IMX_SC_R_DC_0_PLL_0>,
+			<&pd IMX_SC_R_DC_0_PLL_1>;
+	power-domain-names = "dc", "pll0", "pll1";
+	fsl,dpr-channels = <&dc0_dpr1_channel1>, <&dc0_dpr1_channel2>,
+			   <&dc0_dpr1_channel3>, <&dc0_dpr2_channel1>,
+			   <&dc0_dpr2_channel2>, <&dc0_dpr2_channel3>;
+	fsl,pixel-combiner = <&dc0_pc>;
+
+	dpu_disp0: port@0 {
+		reg = <0>;
+
+		dpu_disp0_lvds0_ch0: endpoint@0 {
+			remote-endpoint = <&ldb1_ch0>;
+		};
+
+		dpu_disp0_lvds0_ch1: endpoint@1 {
+			remote-endpoint = <&ldb1_ch1>;
+		};
+
+		dpu_disp0_mipi_dsi: endpoint@2 {
+		};
+	};
+
+	dpu_disp1: port@1 {
+		reg = <1>;
+
+		dpu_disp1_lvds1_ch0: endpoint@0 {
+			remote-endpoint = <&ldb2_ch0>;
+		};
+
+		dpu_disp1_lvds1_ch1: endpoint@1 {
+			remote-endpoint = <&ldb2_ch1>;
+		};
+
+		dpu_disp1_mipi_dsi: endpoint@2 {
+		};
+	};
+};
+
+Freescale i.MX8 PC (Pixel Combiner)
+=============================================
+Required properties:
+- compatible: should be "fsl,<chip>-pixel-combiner"
+- reg: should be register base and length as documented in the
+  datasheet
+- power-domains: phandle pointing to power domain
+
+example:
+
+pixel-combiner@56020000 {
+	compatible = "fsl,imx8qm-pixel-combiner";
+	reg = <0x56020000 0x10000>;
+	power-domains = <&pd IMX_SC_R_DC_0>;
+};
+
+Freescale i.MX8 PRG (Prefetch Resolve Gasket)
+=============================================
+Required properties:
+- compatible: should be "fsl,<chip>-prg"
+- reg: should be register base and length as documented in the
+  datasheet
+- clocks: phandles to the PRG apb and rtram clocks, as described in
+  Documentation/devicetree/bindings/clock/clock-bindings.txt and
+  Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
+- clock-names: should be "apb" and "rtram"
+- power-domains: phandle pointing to power domain
+
+example:
+
+prg@56040000 {
+	compatible = "fsl,imx8qm-prg";
+	reg = <0x56040000 0x10000>;
+	clocks = <&dc0_prg0_lpcg 0>, <&dc0_prg0_lpcg 1>;
+	clock-names = "apb", "rtram";
+	power-domains = <&pd IMX_SC_R_DC_0>;
+};
+
+Freescale i.MX8 DPRC (Display Prefetch Resolve Channel)
+=======================================================
+Required properties:
+- compatible: should be "fsl,<chip>-dpr-channel"
+- reg: should be register base and length as documented in the
+  datasheet
+- fsl,sc-resource: SCU resource number as defined in
+  include/dt-bindings/firmware/imx/rsrc.h
+- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one
+  is the primary PRG and the second one(if available) is the auxiliary PRG
+  which is used to fetch luma chunk of a YUV frame with 2 planars.
+- clocks: phandles to the DPRC apb, b and rtram clocks, as described in
+  Documentation/devicetree/bindings/clock/clock-bindings.txt and
+  Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
+- clock-names: should be "apb", "b" and "rtram"
+- power-domains: phandle pointing to power domain
+
+example:
+
+dpr-channel@560e0000 {
+	compatible = "fsl,imx8qm-dpr-channel";
+	reg = <0x560e0000 0x10000>;
+	fsl,sc-resource = <IMX_SC_R_DC_0_BLIT1>;
+	fsl,prgs = <&dc0_prg2>, <&dc0_prg1>;
+	clocks = <&dc0_dpr0_lpcg 0>,
+		 <&dc0_dpr0_lpcg 1>,
+		 <&dc0_rtram0_lpcg 0>;
+	clock-names = "apb", "b", "rtram";
+	power-domains = <&pd IMX_SC_R_DC_0>;
+};
+
+LCDIF mux display support
+=========================
+
+Required properties:
+- compatible: Should be "fsl,imx-lcdif-mux-display"
+- #address-cells : should be <1>
+- #size-cells : should be <0>
+- pinctrl-names : should be "default"
+- pinctrl-0 : phandle pointing to parallel display pin settings
+- clocks : phandle to the LCD pixel bypass divider clock and the LCD pixel clock
+  as described in Documentation/devicetree/bindings/clock/clock-bindings.txt and
+  Documentation/devicetree/bindings/clock/imx8qxp-clock.txt.
+- clock-names: should be "bypass_div" and "pixel"
+- assigned-clocks: phandle to the LCD pixel selector clock
+- assigned-clock-parents: phandle to the LCD pixel bypass divider clock
+- fsl,lcdif-mux-regs: should be <&lcdif_mux_regs> on i.MX8qxp.
+                      The phandle points to a syscon region containing
+                      LCDIF mux control register.
+- power-domains: phandle pointing to power domain
+- port@[0-1]: Port nodes with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+  Port 0 is the input port connected to the DPU display interface,
+  port 1 is the output port connected to a panel or a bridge.
+Optional properties:
+- fsl,interface-pix-fmt: How this display is connected to the
+  display interface, can be "rgb565", "rgb666" and "rgb888".
+
+example:
+
+display@disp1 {
+	compatible = "fsl,imx-lcdif-mux-display";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif>;
+	clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>,
+		 <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
+	clock-names = "bypass_div", "pixel";
+	assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
+	assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
+	fsl,lcdif-mux-regs = <&lcdif_mux_regs>;
+	fsl,interface-pix-fmt = "rgb666";
+	power-domains = <&pd IMX_SC_R_LCD_0>;
+
+	port@0 {
+		reg = <0>;
+
+		lcd_display_in: endpoint {
+			remote-endpoint = <&dpu_disp1_lcdif>;
+		};
+	};
+
+	port@1 {
+		reg = <1>;
+
+		lcd_display_out: endpoint {
+			remote-endpoint = <&lcd_panel_in>;
+		};
+	};
+};
+
+panel {
+	...
+
+	port {
+		lcd_panel_in: endpoint {
+			remote-endpoint = <&lcd_display_out>;
+		};
+	};
+};
+
 Parallel display support
 ========================
 
diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt
index 8e6e7d797943..df20655866e8 100644
--- a/Documentation/devicetree/bindings/display/imx/ldb.txt
+++ b/Documentation/devicetree/bindings/display/imx/ldb.txt
@@ -9,15 +9,24 @@ nodes describing each of the two LVDS encoder channels of the bridge.
 Required properties:
  - #address-cells : should be <1>
  - #size-cells : should be <0>
- - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
-                Both LDB versions are similar, but i.MX6 has an additional
-                multiplexer in the front to select any of the four IPU display
-                interfaces as input for each LVDS channel.
+ - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or
+                "fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb" or "fsl,imx8mp-ldb".
+                All LDB versions are similar.
+                i.MX6q/dl has an additional multiplexer in the front to select
+                any of the two or four IPU display interfaces as input for each
+                LVDS channel.
+                i.MX8qm LDB supports 10bit RGB input and needs an additional
+                phy.
+                i.MX8qxp and i.MX8mp LDB only supports one LVDS encoder
+                channel(either channel0 or channel1).
  - gpr : should be <&gpr> on i.MX53 and i.MX6q.
          The phandle points to the iomuxc-gpr region containing the LVDS
          control register.
+ - fsl,auxldb : phandle to auxiliary LDB which is used in dual channel mode.
+                Only required by i.MX8qxp.
 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
-                        the display interface selector clocks, as described in
+                        the display interface selector clocks or pixel and
+                        bypass clocks as described in
                         Documentation/devicetree/bindings/clock/clock-bindings.txt
         The following clocks are expected on i.MX53:
                 "di0_pll" - LDB LVDS channel 0 mux
@@ -29,14 +38,27 @@ Required properties:
         On i.MX6q the following additional clocks are needed:
                 "di2_sel" - IPU2 DI0 mux
                 "di3_sel" - IPU2 DI1 mux
+        The following clocks are expected on i.MX8qm and i.MX8qxp:
+                "pixel" - pixel clock
+                "bypass" - bypass clock
+        The following clocks are expected on i.MX8qxp:
+                "aux_pixel" - auxiliary pixel clock in dual channel mode
+                "aux_bypass" - auxiliary bypass clock in dual channel mode
+        The following clocks are expected on i.MX8mp:
+                "ldb" - ldb root clock
         The needed clock numbers for each are documented in
         Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in
-        Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
+        Documentation/devicetree/bindings/clock/imx6q-clock.yaml and in
+        Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt, and in
+        Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
+- power-domains : phandle pointing to power domain, only required by i.MX8qm and
+                  i.MX8qxp.
 
 Optional properties:
- - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
+ - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q, i.MX8qm
+                   i.MX8qxp and i.MX8mp
  - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
-               not used on i.MX6q
+               not used on i.MX6q, i.MX8qm, i.MX8qxp and i.MX8mp
  - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
    be configured - one input will be distributed on both outputs in dual
    channel mode
@@ -57,9 +79,16 @@ Required properties:
    (lvds-channel@[0,1], respectively).
    On i.MX6, there should be four input ports (port@[0-3]) that correspond
    to the four LVDS multiplexer inputs.
-   A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
-   to a panel input port. Optionally, the output port can be left out if
-   display-timings are used instead.
+   On i.MX8qm, the two channels of LDB connect to one display interface of DPU.
+   On i.MX8mp, the two channels of LDB connect to LCDIFv3.
+   A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm,
+   i.MX8qxp and i.MX8mp) must be connected to a panel input port or a bridge
+   input port.
+   Optionally, the output port can be left out if display-timings are used
+   instead.
+ - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm, i.MX8qxp
+         and i.MX8mp.
+ - phy-names: should be "ldb_phy". Valid only on i.MX8qm, i.MX8qxp and i.MX8mp.
 
 Optional properties (required if display-timings are used):
  - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -69,6 +98,7 @@ Optional properties (required if display-timings are used):
                       This describes how the color bits are laid out in the
                       serialized LVDS signal.
  - fsl,data-width : should be <18> or <24>
+                    Additionally, <30> for i.MX8qm.
 
 example:
 
diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
index 0091df9dd73b..aa8fd03c93ba 100644
--- a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -46,6 +46,8 @@ properties:
       - description: RTRAM clock
       - description: Pixel clock, can be driven either by HDMI phy clock or MIPI
       - description: DTRC clock, needed by video decompressor
+      - description: PLL source clock, usually VIDEO2_PLL, used when output is HDMI;
+      - description: PLL PHY reference clock, used when output is HDMI;
 
   clock-names:
     items:
@@ -54,6 +56,8 @@ properties:
       - const: rtrm
       - const: pix
       - const: dtrc
+      - const: pll_src
+      - const: pll_phy_ref
 
   assigned-clocks:
     items:
@@ -91,8 +95,10 @@ examples:
         interrupt-parent = <&irqsteer>;
         clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
                  <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
-                 <&clk IMX8MQ_CLK_DISP_DTRC>;
-        clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+                 <&clk IMX8MQ_CLK_DISP_DTRC>, <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
+                 <&clk IMX8MQ_CLK_PHY_27MHZ>;
+        clock-names = "apb", "axi", "rtrm", "pix", "dtrc",
+                      "pll_src", "pll_phy_ref";
         assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
                           <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8ulp-dcnano.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8ulp-dcnano.yaml
new file mode 100644
index 000000000000..591bd227f7b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8ulp-dcnano.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/nxp,imx8ulp-dcnano.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8ulp DCNANO display controller
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  The NXP i.MX8ulp DCNANO display controller is a high-performance graphics
+  core that can be used for reading rendered images from the frame buffer.
+  In addition to providing hardware cursor patterns, the display controller
+  performs format conversions, dithering and gamma corrections.  The display
+  controller supports either Display Pixel Interface-2(DPI-2) or Display Bus
+  Interface 2.0(DBI-2).
+
+properties:
+  compatible:
+    const: nxp,imx8ulp-dcnano
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: axi
+      - const: ahb
+      - const: pixel
+
+  resets:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  assigned-clocks: true
+  assigned-clock-parents: true
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The DCNANO DPI-2 output port node.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The DCNANO DBI-2 output port node.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx8ulp-clock.h>
+    #include <dt-bindings/power/imx8ulp-power.h>
+    #include <dt-bindings/reset/imx8ulp-pcc-reset.h>
+    dcnano: display-controller@2e050000 {
+        compatible = "nxp,imx8ulp-dcnano";
+        reg = <0x2e050000 0x10000>;
+        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>,
+                 <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>,
+                 <&pcc5 IMX8ULP_CLK_DC_NANO>;
+        clock-names = "axi", "ahb", "pixel";
+        resets = <&pcc5 PCC5_DC_NANO_SWRST>;
+        power-domains = <&scmi_devpd IMX8ULP_PD_DCNANO>;
+        assigned-clocks = <&pcc5 IMX8ULP_CLK_DC_NANO>;
+        assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            dcnano_dpi: port@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0>;
+
+                dcnano_dpi_to_mipi_dsi: endpoint@0 {
+                    reg = <0>;
+                };
+
+                dcnano_dpi_to_disp: endpoint@1 {
+                    reg = <1>;
+                };
+            };
+
+            dcnano_dbi: port@1 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <1>;
+
+                dcnano_dbi_to_mipi_dsi: endpoint@0 {
+                    reg = <0>;
+                };
+
+                dcnano_dbi_to_disp: endpoint@1 {
+                    reg = <1>;
+                };
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt b/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt
new file mode 100644
index 000000000000..b245b4d68d0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt
@@ -0,0 +1,9 @@
+Japan Display Inc. 10.1" WUXGA (1920x1200) TFT LCD panel
+
+The panel has dual LVDS channels.
+
+Required properties:
+- compatible: should be "jdi,tx26d202vm0bwa"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml b/Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml
index 745dd247c409..6a6f54dd375e 100644
--- a/Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml
+++ b/Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/display/panel/raydium,rm67191.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Raydium RM67171 OLED LCD panel with MIPI-DSI protocol
+title: Raydium RM67171/RM67199 OLED LCD panel with MIPI-DSI protocol
 
 maintainers:
   - Robert Chiras <robert.chiras@nxp.com>
@@ -14,7 +14,9 @@ allOf:
 
 properties:
   compatible:
-    const: raydium,rm67191
+    items:
+      - const: raydium,rm67191
+      - const: raydium,rm67199
 
   reg: true
   port: true
@@ -37,7 +39,8 @@ properties:
       0 - burst-mode
       1 - non-burst with sync event
       2 - non-burst with sync pulse
-    enum: [0, 1, 2]
+      3 - command mode
+    enum: [0, 1, 2, 3]
 
 required:
   - compatible
diff --git a/Documentation/devicetree/bindings/display/panel/rocktech,himax8394f.yaml b/Documentation/devicetree/bindings/display/panel/rocktech,himax8394f.yaml
new file mode 100644
index 000000000000..4637a7159801
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/rocktech,himax8394f.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/rocktech,himax8394f.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rocktech Himax8394f 720x1280 TFT LCD panel
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description:
+  Rocktech Himax8394f is a 720x1280 TFT LCD panel
+  connected using a MIPI-DSI video interface.
+
+allOf:
+  - $ref: panel-common.yaml#
+
+properties:
+  compatible:
+    const: rocktech,himax8394f
+
+  reg:
+    maxItems: 1
+    description: DSI virtual channel
+
+  himax,dsi-lanes:
+    description: Number of DSI lanes to be used must be <1> or <2> or <3> or <4>
+    enum: [1, 2, 3, 4]
+
+  enable-gpios: true
+  port: true
+
+  vcc-supply:
+    description: A typical 2.8V supply(minimum 2.5V, maximum 3.6V).
+
+  iovcc-supply:
+    description: A typical 1.8V supply(minimum 1.65V, maximum 3.6V).
+
+  reset-gpios:
+    maxItems: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - himax,dsi-lanes
+  - vcc-supply
+  - iovcc-supply
+
+examples:
+  - |
+    dsi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      panel@0 {
+        compatible = "rocktech,himax8394f";
+        reg = <0>;
+        himax,dsi-lanes = <2>;
+        enable-gpios = <&pca6416_1 9 GPIO_ACTIVE_HIGH>;
+        reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>;
+        vcc-supply = <&reg_5v>;
+        iovcc-supply = <&reg_5v>;
+      };
+    };
+...
diff --git a/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml b/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml
new file mode 100644
index 000000000000..bc17dfcd80e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/wks,101wx001.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: WKS 101WX001 10.1" WXGA TFT LCD panel
+
+description:
+  The WKS 101WX001 is a 10.1" WXGA (1280 x 800) TFT LCD panel with a 24-bit RGB
+  parallel data interface.
+
+maintainers:
+  - Robert Chiras <robert.chiras@nxp.com>
+
+allOf:
+  - $ref: panel-common.yaml#
+
+properties:
+  compatible:
+    const: wks,101wx001
+
+  label: false
+  port: true
+
+  vcc-supply:
+    description: 5v analog power regulator
+
+  blctr-gpios:
+    description: GPIO used for BL_CNTR pin, controlling the panel backlight
+                 (this is not a pwm backlight, it's only a GPIO controlled
+                 backlight)
+    maxItems: 1
+
+  pinctrl-assert-gpios:
+    description: Default states for various gpios used as selectors for on-board
+                 muxes
+
+required:
+  - compatible
+  - port
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    panel {
+      compatible = "wks,101wx001";
+      blctr-gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+      pinctrl-assert-gpios = <&gpiob 3 GPIO_ACTIVE_LOW>,
+                             <&gpiob 4 GPIO_ACTIVE_LOW>,
+                             <&gpiob 6 GPIO_ACTIVE_LOW>,
+                             <&gpiob 7 GPIO_ACTIVE_LOW>,
+                             <&gpiob 8 GPIO_ACTIVE_LOW>;
+
+      port {
+        panel_in: endpoint {
+          remote-endpoint = <&lcdif_out>;
+        };
+      };
+    };