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authorVinod Koul <vkoul@kernel.org>2018-12-31 19:32:27 +0530
committerVinod Koul <vkoul@kernel.org>2018-12-31 19:32:27 +0530
commit69ca36b3d629f1fcdaa9e7abb8b6b2084ff947dd (patch)
tree71ca2c76ae26388aa362295b7b7cad3d00bcbf8a /Documentation
parent990beed934fc4568d6e76a5117e71a92fd9fd9d1 (diff)
parent32e74aabebc8d045a11452d2de0ac9d2625fcd45 (diff)
Merge branch 'topic/uniphier' into for-linus
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt25
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+UniPhier Media IO DMA controller
+
+This works as an external DMA engine for SD/eMMC controllers etc.
+found in UniPhier LD4, Pro4, sLD8 SoCs.
+
+Required properties:
+- compatible: should be "socionext,uniphier-mio-dmac".
+- reg: offset and length of the register set for the device.
+- interrupts: a list of interrupt specifiers associated with the DMA channels.
+- clocks: a single clock specifier.
+- #dma-cells: should be <1>. The single cell represents the channel index.
+
+Example:
+ dmac: dma-controller@5a000000 {
+ compatible = "socionext,uniphier-mio-dmac";
+ reg = <0x5a000000 0x1000>;
+ interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+ <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
+ clocks = <&mio_clk 7>;
+ #dma-cells = <1>;
+ };
+
+Note:
+In the example above, "interrupts = <0 68 4>, <0 68 4>, ..." is not a typo.
+The first two channels share a single interrupt line.