Merge branch 'dma/next' into next

* dma/next: (52 commits)
  LF-301: dmaengine: imx-sdma: Add once more loading firmware
  LF-246: dmaengine: imx-sdma: correct is_ram_script checking
  dma: caam: fix compilation error
  dma: caam: add dma memcpy driver
  dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
  ...

3 files changed, 109 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
new file mode 100644
index 000000000000..8fe82ce63632
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
@@ -0,0 +1,82 @@
+* Freescale enhanced Direct Memory Access(eDMA-v3) Controller
+
+  The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated
+  on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by
+  programmble memory-mapped registers. Specific DMA request source has fixed channel.
+
+* eDMA Controller
+Required properties:
+- compatible :
+	- "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC
+	- "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM
+- reg : Specifies base physical address(s) and size of the eDMA channel registers.
+	Each eDMA channel has separated register's address and size.
+- interrupts : A list of interrupt-specifiers, each channel has one interrupt.
+- interrupt-names : Should contain below template:
+	"edmaX-chanX-Xx"
+	     |     | |---> receive/transmit, r or t
+	     |     |---> channel id, the max number is 32
+	     |---> edma controller instance, 0, 1, 2,..etc
+
+- #dma-cells : Must be <3>.
+	The 1st cell specifies the channel ID.
+	The 2nd cell specifies the channel priority.
+	The 3rd cell specifies the channel attributes which include below:
+	BIT(0): transmit or receive:
+		0: transmit, 1: receive.
+	BIT(1): local or remote access:
+		0: local, 1: remote.
+	BIT(2): dualfifo case or not(only in Audio cyclic now):
+		0: not dual fifo case, 1: dualfifo case.
+	See the SoC's reference manual for all the supported request sources.
+- dma-channels : Number of channels supported by the controller
+- power-domains: Power domains for edma channel used.
+- power-domain-names: Power domains name for edma channel used.
+
+Examples:
+edma0: dma-controller@40018000 {
+	compatible = "fsl,imx8qm-edma";
+	reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
+	      <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
+	      <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
+	      <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
+	#dma-cells = <3>;
+	dma-channels = <4>;
+	interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx",
+			  "edma0-chan14-rx", "edma0-chan15-tx";
+	power-domains = <&pd IMX_SC_R_DMA_0_CH12>,
+			<&pd IMX_SC_R_DMA_0_CH13>,
+			<&pd IMX_SC_R_DMA_0_CH14>,
+			<&pd IMX_SC_R_DMA_0_CH15>;
+	power-domain-names = "edma0-chan12", "edma0-chan13",
+			     "edma0-chan14", "edma0-chan15";
+	status = "okay";
+};
+
+* DMA clients
+DMA client drivers that uses the DMA function must use the format described
+in the dma.txt file, using a three-cell specifier for each channel: the 1st
+specifies the channel number, the 2nd specifies the priority, and the 3rd
+specifies the channel type is for transmit or receive: 0: transmit, 1: receive.
+
+Examples:
+lpuart1: serial@5a070000 {
+	compatible = "fsl,imx8qm-lpuart";
+	reg = <0x0 0x5a070000 0x0 0x1000>;
+	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-parent = <&gic>;
+	clocks = <&clk IMX8QM_UART1_CLK>;
+	clock-names = "ipg";
+	assigned-clock-names = <&clk IMX8QM_UART1_CLK>;
+	assigned-clock-rates = <80000000>;
+	power-domains = <&pd IMX_SC_R_UART_1>,
+	power-domain-names = "uart";
+	dma-names = "tx","rx";
+	dmas = <&edma0 15 0 0>,
+		<&edma0 14 0 1>;
+	status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
index 7bd8847d6394..d10a9c1d2ce6 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
@@ -16,6 +16,21 @@ Optional properties:
 - #dma-channels : Number of DMA channels supported. Should be 16.
 - #dma-requests : Number of DMA requests supported.
 
+* DMA capability limitation
+
+Specify the DMA capability limitations.
+For example, some SoCs only support up to 32bit DMA capability, although
+they are 64bit SoCs.
+
+- only-dma-mask32: 1 means that the SoCs only suppot up to 32bit DMA
+  capability.
+
+Example:
+	dma_cap: dma_cap {
+		compatible = "dma-capability";
+		only-dma-mask32 = <1>;
+	};
+
 Example:
 
 	dma: dma@10001000 {
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index 9d8bbac27d8b..ebbf7cfb1241 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -9,6 +9,8 @@ Required properties:
       "fsl,imx53-sdma"
       "fsl,imx6q-sdma"
       "fsl,imx7d-sdma"
+      "fsl,imx6sx-sdma"
+      "fsl,imx6ul-sdma"
       "fsl,imx8mq-sdma"
   The -to variants should be preferred since they allow to determine the
   correct ROM script addresses needed for the driver to work without additional
@@ -51,8 +53,14 @@ The full ID of peripheral types can be found below.
 	22	SSI Dual FIFO	(needs firmware ver >= 2)
 	23	Shared ASRC
 	24	SAI
+	25	HDMI Audio
 
-The third cell specifies the transfer priority as below.
+The third cell specifies the transfer priority and software done
+as below.
+
+	Bit31: sw_done
+	Bit15~Bit8: selector
+	Bit7~Bit0: priority level
 
 	ID	transfer priority
 	-------------------------
@@ -60,6 +68,9 @@ The third cell specifies the transfer priority as below.
 	1	Medium
 	2	Low
 
+For example: 0x80000000 means sw_done enabled for done0 sector and
+	High priority for PDM on i.mx8mm.
+
 Optional properties:
 
 - gpr : The phandle to the General Purpose Register (GPR) node.