diff options
| author | Robin Gong <yibin.gong@nxp.com> | 2017-11-16 17:23:40 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:29:14 +0800 |
| commit | e2db418134136018915c09a3a20620a9c76e6726 (patch) | |
| tree | 8ec5d65316290e1335df1cf9b70486f1685e001d /Documentation | |
| parent | 9c17d58c0277702721f4b875b0fd76b0d2009a99 (diff) | |
MLK-16841-1: dma: imx-sdma: add clock ration 1:1 check
On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted,
since SDMA clock ration has to be increased to 250Mhz, AHB can't reach
to 500Mhz, so use 1:1 instead.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index 0839b70f0261..81b8cad86d17 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt @@ -69,6 +69,7 @@ Optional properties: reg is the GPR register offset. shift is the bit position inside the GPR register. val is the value of the bit (0 or 1). +- fsl,ratio-1-1: AHB/SDMA core clock ration 1:1, 2:1 without this. Examples: |