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authorLinus Torvalds <torvalds@linux-foundation.org>2011-10-25 10:18:27 +0200
committerLinus Torvalds <torvalds@linux-foundation.org>2011-10-25 10:18:27 +0200
commit1bc67188c3843b8e16caaa8624beeb0e2823c1f8 (patch)
tree76299c9a161e2f179bf8bbd6c2b6c60191a9c76d /Documentation
parent36b8d186e6cc8e32cb5227f5645a58e1bc0af190 (diff)
parentbdf4e9482360a3ddc1619efbd5d1c928ede8c3fa (diff)
Merge branch 'for-linus' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'for-linus' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: (81 commits) ARM: 7133/1: SMP: fix per cpu timer setup before the cpu is marked online ARM: 7129/1: Add __arm_ioremap_exec for mapping external memory as MT_MEMORY ARM: 7136/1: pl330: Fix a race condition ARM: smp: fix clipping of number of CPUs ARM: 7137/1: Fix error upon adding LL debug ARM: Add a few machine types to mach-types ARM: 7130/1: dev_archdata: add private iommu extension ARM: 7125/1: Add unwinding annotations for 64bit division functions ARM: 7120/1: remove bashism in check for multiple zreladdrs ARM: 7118/1: rename temp variable in read*_relaxed() ARM: 6217/4: mach-realview: expose PB1176 ROM using physmap and map_rom ARM: 7098/1: kdump: copy kernel relocation code at the kexec prepare stage ARM: 7062/1: cache: detect PIPT I-cache using CTR ARM: platform fixups: remove mdesc argument to fixup function ARM: 7017/1: Use generic BUG() handler ARM: 7102/1: mach-integrator: update defconfig ARM: 7087/2: mach-integrator: get timer frequency from clock ARM: 7086/2: mach-integrator: modernize clock event registration ARM: 7085/2: mach-integrator: clockevent supports oneshot mode ARM: 7084/1: mach-integrator: retire some timer macros ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/l2cc.txt44
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diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
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+* ARM L2 Cache Controller
+
+ARM cores often have a separate level 2 cache controller. There are various
+implementations of the L2 cache controller with compatible programming models.
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+ "arm,pl310-cache"
+ "arm,l220-cache"
+ "arm,l210-cache"
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+ registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Minimum valid values are 1. Controllers
+ without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Controllers without setup latency control
+ should use 0. Controllers without separate read and write Tag RAM latency
+ values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges : <start length> Starting address and length of window to
+ filter. Addresses in the filter window are directed to the M1 port. Other
+ addresses will go to the M0 port.
+- interrupts : 1 combined interrupt.
+
+Example:
+
+L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfff12000 0x1000>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-latency = <0x80000000 0x8000000>;
+ cache-unified;
+ cache-level = <2>;
+ interrupts = <45>;
+};