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| author | Li Jun <jun.li@freescale.com> | 2015-05-20 14:28:26 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 10:59:12 -0600 |
| commit | 70ddea34e81412afa10d446d9073a718593e1076 (patch) | |
| tree | d5c95a8144d2a23d0db06f3b334bc93ac42fbbd0 /Documentation | |
| parent | b7fd89b0070bf8e589edd02809cb6a5e1f11690a (diff) | |
MLK-10930-1 doc: usb: ci-hdrc-imx: add phy-clkgate-delay-us property
It's optional, for delay time between putting phy into low power mode
and turn off PHY clock.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit cccad79e056098827e1f5006d159f065889e4b8e)
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt index ce547ff9e279..2f1a4224c0e0 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt @@ -32,6 +32,8 @@ Optional properties: 0 <= osc-clkgate-delay <= 7. - maximum-speed: limit the maximum connection speed to "full-speed". - tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts +- phy-clkgate-delay-us: the delay time(us) between putting phy into low power + mode and gate phy clock. Examples: usb@02184000 { /* USB OTG */ @@ -50,4 +52,5 @@ usb@02184000 { /* USB OTG */ osc-clkgate-delay = <0x3>; maximum-speed = "full-speed"; tpl-support; + phy-clkgate-delay-us = <400>; }; |