diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2013-05-12 16:56:28 +0530 |
|---|---|---|
| committer | Riham Haidar <rhaidar@nvidia.com> | 2013-09-16 12:28:14 -0700 |
| commit | a347efa9c3014e6418dc9cd7171deff3c9e41460 (patch) | |
| tree | 50e21fd806a1c97c3663552f9a54e4458928020f /Documentation | |
| parent | cf52b7b238c044b41b3b21ebcf8992160eae5ce6 (diff) | |
ARM: tegra: roth: Mask HS200 mode support
Mask HS200 mode support for sdmmc4.
In DDR50 mode for eMMC can support max clock of 52MHz. For Tegra sdmmc
controllers, the host clock in ddr mode should be double that of the
eMMC device. Taking into consideration the dvfs tables, limiting ddr
mode clock to 51MHz to allow for lower core voltages to set even when
sdmmc4 clock is ON.
Bug 1287739
BUg 1324297
Reviewed-on: http://git-master/r/230048
(cherry picked from commit d7214ec63a22383be14ee4f1fb424ad8e0f00364)
Change-Id: Ib04dce91d771ab5505dd67ea3a8d5c704d0b499e
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Change-Id: I539439a3ccff3f75a25ea13198aa6267a7293dca
Reviewed-on: http://git-master/r/274993
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions