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authorLaxman Dewangan <ldewangan@nvidia.com>2013-02-19 17:51:36 +0530
committerDan Willemsen <dwillemsen@nvidia.com>2013-09-14 01:13:11 -0700
commit2686d090e54a4d142098ab82b93f271a0b55731e (patch)
tree83d022db4e2ea5a2e0601b2b1617f6a2bb6e0d35 /Documentation
parent1a34360579cffb41f08465b7e158841d8228dfaf (diff)
spi: tegra114: add spi driver
Add spi driver for NVIDIA's Tegra114 spi controller. This controller is different than the older SoCs spi controller and there is a change in register interface also. This driver supports the: - non DMA based transfer for smaller transfer i.e. less than FIFO depth. - APB DMA based transfer for lager transfer i.e. more than FIFO depth. - Runtime PM for clock gating. - registration through DT and platform board files. Change-Id: I30ab59a29d80b191843878994227945261ae8e17 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/202032 Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com> (cherry picked from commit 8b21af40fc68e280a1e7f0168928d1b97b61b6ba)
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt29
1 files changed, 29 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt b/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt
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index 000000000000..8a93aacd8d86
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+++ b/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt
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+NVIDIA Tegra114 SPI controller.
+
+Required properties:
+- compatible : should be "nvidia,tegra114-spi".
+- reg: Should contain SPI registers location and length.
+- interrupts: Should contain SPI interrupts.
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+ request selector for this SPI controller.
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+Optional properties:
+- nvidia,clock-always-on: Enable clock of spi always.
+
+Example:
+
+spi@7000d600 {
+ compatible = "nvidia,tegra114-spi";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-request-selector = <&apbdma 16>;
+ spi-max-frequency = <25000000>;
+ nvidia,clock-always-on;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+};
+