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| author | Arnd Bergmann <arnd@arndb.de> | 2013-06-21 15:28:16 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2013-06-21 15:28:16 +0200 |
| commit | 5b520c94b30c643f24f43c79aa638c0a1fe3b15c (patch) | |
| tree | 84f50948f368e87153dba160c77ba7e657445366 /Documentation | |
| parent | 076919a6e0154f06221e02f9e58b14eb1ed9e019 (diff) | |
| parent | c4fa4946f177ae214523586cd794ac18d34b1430 (diff) | |
Merge tag 'renesas-dt2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
From Simon Horman:
Second Round of Renesas ARM-based SoC DT updates for v3.11
* Increased DT coverage for renesas-intc-irqpin
by Guennadi Liakhovetski
* Clean up of address format used in sh73a0 dtsi file
by Guennadi Liakhovetski
* tag 'renesas-dt2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: irqpin: add a DT property to enable masking on parent
ARM: shmobile: sh73a0: remove "0x" prefix from DT node names
irqchip: renesas-intc-irqpin: DT binding for sense bitfield width
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file mode 100644 index 000000000000..1f8b0c507c26 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt @@ -0,0 +1,16 @@ +DT bindings for the R-/SH-Mobile irqpin controller + +Required properties: + +- compatible: has to be "renesas,intc-irqpin" +- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in + interrupts.txt in this directory + +Optional properties: + +- any properties, listed in interrupts.txt, and any standard resource allocation + properties +- sense-bitfield-width: width of a single sense bitfield in the SENSE register, + if different from the default 4 bits +- control-parent: disable and enable interrupts on the parent interrupt + controller, needed for some broken implementations |