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authorLiu Ying <victor.liu@nxp.com>2017-05-23 14:55:17 +0800
committerLeonard Crestez <leonard.crestez@nxp.com>2018-08-24 12:41:33 +0300
commitc86077ec863d29481cf23b88ba815d987ab683ed (patch)
treeb8d9ac08c5a7b97bbc5d18e9e9ba03e521723aa0 /Documentation
parent76a9ac9de9d7e83fa72ed6696434b98ab9708af3 (diff)
MLK-15001-22 phy: Add Mixel LVDS combo PHY support
This patch adds Mixel LVDS combo PHY support(MIPI DSI and LVDS combo). This LVDS PHY supports one LVDS channel in single mode and two channels in dual mode. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/phy/mixel,lvds-combo-phy.txt20
1 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-combo-phy.txt b/Documentation/devicetree/bindings/phy/mixel,lvds-combo-phy.txt
new file mode 100644
index 000000000000..7d36747871fa
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+++ b/Documentation/devicetree/bindings/phy/mixel,lvds-combo-phy.txt
@@ -0,0 +1,20 @@
+Mixel LVDS combo PHY
+
+Required properties:
+- compatible: must be "mixel,lvds-combo-phy".
+- reg: offset and length of the register block.
+- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
+- clocks: clock phandle and specifier pair.
+- clock-names: string, clock input name, must be "phy".
+- power-domains: phandle pointing to power domain.
+
+Example:
+ ldb1_phy: ldb_phy@56221000 {
+ compatible = "mixel,lvds-combo-phy";
+ reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>;
+ clock-names = "phy";
+ power-domains = <&pd_mipi_dsi0>;
+ status = "disabled";
+ };