ENGR00309977-2 ARM: imx6q/sl: Set SPDIF clock to 22736841Hz

Since we no longer use clk_set_rate() in spdif driver, the rate we provide
to it on imx6q/sl platforms is no more contented for its supporting sample
rates.

By setting the clock to 22736841Hz, we can get the sample rates:
48008Hz for 48000Hz
32005Hz for 32000Hz
43859Hz for 44100Hz

The results for 48KHz and 32KHz has changed comparing to the previous
release, but the one for 44100Hz has a bit lose even though it should
be the best we can get based on the current clock rate. If user want
to playback a perfect 44100Hz, they need to change the parent clock
rate.

Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit f12e2ea9c6c5557adb3bbe26c51021978f2c8d99)

0 files changed, 0 insertions, 0 deletions