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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-04-04 14:23:55 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-04-04 14:23:55 +0200 |
| commit | 837e5b8e0685e2e4974e5a86dfd7cbf5802e1422 (patch) | |
| tree | 1b4e116a20e6fdef01a1fc9ee7b46aeeecc23ed0 /arch/arc/include/asm/cacheflush.h | |
| parent | 418f717cce5834203e24368717f542360b020681 (diff) | |
| parent | 61a4577c9a4419b99e647744923517d47255da35 (diff) | |
Merge tag 'v4.4.59' into toradex_vf_4.4-next
This is the 4.4.59 stable release
Diffstat (limited to 'arch/arc/include/asm/cacheflush.h')
| -rw-r--r-- | arch/arc/include/asm/cacheflush.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h index fbe3587c4f36..56aeb5efe604 100644 --- a/arch/arc/include/asm/cacheflush.h +++ b/arch/arc/include/asm/cacheflush.h @@ -85,6 +85,10 @@ void flush_anon_page(struct vm_area_struct *vma, */ #define PG_dc_clean PG_arch_1 +#define CACHE_COLORS_NUM 4 +#define CACHE_COLORS_MSK (CACHE_COLORS_NUM - 1) +#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK) + /* * Simple wrapper over config option * Bootup code ensures that hardware matches kernel configuration @@ -94,8 +98,6 @@ static inline int cache_is_vipt_aliasing(void) return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); } -#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1) - /* * checks if two addresses (after page aligning) index into same cache set */ |