diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2009-03-10 10:25:05 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2009-03-10 10:25:05 +0000 |
| commit | d379f9d8cbfa8e70273e40dc7904bf09c18bc85e (patch) | |
| tree | 680dc57057fd7c2c0e5001f61355cf642b6087d4 /arch/arm/Kconfig | |
| parent | ce67a78251af291d6aae52301b536b6bcef9a8d0 (diff) | |
Data written to the L2 cache can be overwritten with stale data on Cortex-A8
This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It
configures the L2 cache auxiliary control register so that the Write
Allocate mode for the L2 cache is disabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43a7330558e2..bf27b6db52af 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -721,6 +721,17 @@ config ARM_ERRATA_458693 different cache line. This false hazard might then cause a processor deadlock. +config ARM_ERRATA_460075 + bool "Data written to the L2 cache can be overwritten with stale data on Cortex-A8" + depends on CPU_V7 + default n + help + This option enables the workaround for the 458692 Cortex-A8 + (r2p0) erratum. Any asynchronous access to the L2 cache may + encounter a situation in which recent store transactions to + the L2 cache are lost and overwritten with stale memory + contents from external memory. + endmenu source "arch/arm/common/Kconfig" |