diff options
| author | Bo Yan <byan@nvidia.com> | 2013-03-25 13:27:41 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:05:51 -0700 |
| commit | 1ca903d35d842db294fc5045cf6ef184b102e8b4 (patch) | |
| tree | 0f382b641becf41565b8ec00a44970c407576bf5 /arch/arm/Kconfig | |
| parent | 58e97f7db8a2e3b03162f4e6b7651fde736206d0 (diff) | |
ARM errata: Writing ACTLR.SMP when the L2 cache has been idle for an extended period may not work correctly
This workaround is for ARM errata 799270 which is applicable to
Cortex-A15 up to revision R2P4. The workaround is to read from
a device register and create a data dependency between this read
and the modification of ACTLR.
Change-Id: I26813f17a8a9c6a90446ddeb943ef318e3c69770
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/212770
(cherry picked from commit 2340401e2dec7228bcc5d9074c310d0146454736)
Reviewed-on: http://git-master/r/213135
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a5b2d02c3655..5bac50c002bf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1411,6 +1411,21 @@ config ARM_ERRATA_798181 which sends an IPI to the CPUs that are running the same ASID as the one being invalidated. +config ARM_ERRATA_799270 + bool "ARM errata: Writing ACTLR.SMP when the L2 cache has been idle for an extended period may not work correctly" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 799270 Cortex-A15 (r2p0, + r2p1, r2p2, r2p3, r2p4) erratum. If the L2 cache logic clock is + stopped because of L2 inactivity, setting or clearing the ACTLR.SMP + bit might not be effective. The bit is modified in the ACTLR, meaning + a read of the register returns the updated value. However the logic + that uses that bit retains the previous value. The workaround is to + do a memory read to a memory location with Non-cacheable, Strongly- + ordered, or Device memory attributes. A dependency must be created + between the returning load data and the MCR instruction that sets the + ACTLR.SMP bit. + endmenu source "arch/arm/common/Kconfig" |