diff options
| author | Krishna Reddy <vdumpa@nvidia.com> | 2012-12-12 12:16:46 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:46:29 -0700 |
| commit | 320d8188312e61ab365fbe0f8b1686f39884d077 (patch) | |
| tree | 6ae2b1c90a6ca0666a89237496c32aab9a4d3a26 /arch/arm/Kconfig | |
| parent | 45bcf888f461f07c09bbcd3e1c55b5046fc286be (diff) | |
arm: errata: 761320: Full cache line writes to the same memory region from at least two processors might deadlock processor
Under very rare circumstances, full cache line writes
from (at least) 2 processors on cache lines in hazard with
other requests may cause arbitration issues in the SCU,
leading to processor deadlock. This erratum can be
worked around by setting bit[21] of the undocumented
Diagnostic Control Register to 1.
Change-Id: I83f919ead5ef4f90f50fa3f38f2cc31ab6bfc31e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/170582
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 28da4918f9f0..38f99cfb2507 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1368,6 +1368,17 @@ config ARM_ERRATA_752520 and MMU are enabled, with the TLB descriptors marked as L1 cacheable, so that Page Table Walks are performed as cache linefills. +config ARM_ERRATA_761320 + bool "Full cache line writes to the same memory region from at least two processors might deadlock processor" + depends on CPU_V7 && SMP + help + Under very rare circumstances, full cache line writes + from (at least) 2 processors on cache lines in hazard with + other requests may cause arbitration issues in the SCU, + leading to processor deadlock. This erratum can be + worked around by setting bit[21] of the undocumented + Diagnostic Control Register to 1. + config PL310_ERRATA_769419 bool "PL310 errata: no automatic Store Buffer drain" depends on CACHE_L2X0 |