diff options
| author | Bo Yan <byan@nvidia.com> | 2013-03-25 14:21:30 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:06:44 -0700 |
| commit | 9100bfcc916a840c7ae8130a7b61d22b2094e357 (patch) | |
| tree | ec7377008682d4a19065780e7423e4ab1ec6a894 /arch/arm/Kconfig | |
| parent | fdf2ffe7ef1e53195ea29309a506ee786da2c10f (diff) | |
ARM errata: A memory read can stall indefinitely in the L2 cache
Define a configuration option for platform to implement
Change-Id: I352c644a33ebbf809e450004a01394f07f2903b7
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/212781
(cherry picked from commit 91250495671135d9d815da3e65777844957216e1)
Reviewed-on: http://git-master/r/216183
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5bac50c002bf..d93666058e34 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1426,6 +1426,18 @@ config ARM_ERRATA_799270 between the returning load data and the MCR instruction that sets the ACTLR.SMP bit. +config ARM_ERRATA_798870 + bool "ARM errata: A memory read can stall indefinitely in the L2 cache" + depends on CPU_V7 + help + If back-to-back speculative cache line fills (fill A and fill B) + are issued from the L1 data cache of a CPU to the L2 cache, the + second request (fill B) is then cancelled, and the second request + would have detected a hazard against a recent write or eviction + (write B) to the same cache line as fill B, then the L2 logic might + deadlock. The workaround is to let a secondary CPU go through reset + cycle periodically which can restart L2 clock. + endmenu source "arch/arm/common/Kconfig" |