diff options
| author | vdumpa <vdumpa@nvidia.com> | 2011-04-27 11:11:44 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 01:32:23 -0700 |
| commit | b118f1f73eba23ab039705d9b593f1b2876048a7 (patch) | |
| tree | 36f97736380a9d2f13a2852108189c6bedc1ee35 /arch/arm/Kconfig | |
| parent | fb828c70373de873d305efc64a5cefbce0db87a7 (diff) | |
ARM: errata: 752520: Faulty arbitration between PLD and Cacheable TLB requests may create a system deadlock.
Under rare circumstances, PLDs may interfere with a Cacheable page table walk,
creating a processor deadlock. The erratum can only happen when the Data Cache
and MMU are enabled, with the TLB descriptors marked as L1 cacheable,
so that Page Table Walks are performed as cache linefills.
This workaround sets a bit in the diagnostic register of the Cortex-A9,
causing PLD operations treated as NOP.
(cherry-picked from b501cafea7328bc578f67e3e846ab9d25b7ec1b0)
Change-Id: Ic4039b83de43530bae7ce705162441bea74e1e98
Reviewed-on: http://git-master/r/54095
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Ra35e48e21c1d62b6480a9d67d1413dd5d0df3f53
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index be2af4d57863..0f8757aa347a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1348,6 +1348,15 @@ config ARM_ERRATA_720791 This workaround disables gating the Core clock when the Instruction side is waiting for a Page Table Walk answer or linefill completion. +config ARM_ERRATA_752520 + bool "ARM errata: Faulty arbitration between PLD and Cacheable TLB requests may create a system deadlock" + depends on CPU_V7 + help + Under rare circumstances, PLDs may interfere with a Cacheable page table walk, + creating a processor deadlock. The erratum can only happen when the Data Cache + and MMU are enabled, with the TLB descriptors marked as L1 cacheable, + so that Page Table Walks are performed as cache linefills. + config PL310_ERRATA_769419 bool "PL310 errata: no automatic Store Buffer drain" depends on CACHE_L2X0 |