diff options
| author | Dan Willemsen <dwillemsen@nvidia.com> | 2013-08-20 00:32:03 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 01:32:20 -0700 |
| commit | d9b1f8b29d026c7025813be97ed471b5b530d1e0 (patch) | |
| tree | 0ad29e5769e1a5158fabc4a3743148c15d17212e /arch/arm/Kconfig | |
| parent | 6bd3f7e3672575a264e1ab00c7766670ea2debee (diff) | |
ARM: Cortex-A9: Enable dynamic clock gating
Enable dynamic high level clock gating for Cortex-A9 CPUs, as
described in 2.3.3 "Dynamic high level clock gating" of the
Cortex-A9 TRM. This may cut the clock of the integer core,
system control block, and Data Engine in certain conditions.
Add ARM errata 720791 to avoid corrupting the Jazelle
instruction stream on earlier Cortex-A9 revisions.
Original-Change-Id: I48e51d907e593f26982ea91b0a811553f68e3c86
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Rebase-Id: R7ae4d4825e9171bca2471fe776ecf363e75b9ca6
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 162f27ad6f2c..be2af4d57863 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1338,6 +1338,16 @@ config ARM_ERRATA_764369 relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU. +config ARM_ERRATA_720791 + bool "ARM errata: Dynamic high-level clock gating corrupts the Jazelle instruction stream" + depends on CPU_V7 + help + This option enables the workaround for the 720791 Cortex-A9 + (r1p0..r1p2) erratum. The Jazelle instruction stream may be + corrupted when dynamic high-level clock gating is enabled. + This workaround disables gating the Core clock when the Instruction + side is waiting for a Page Table Walk answer or linefill completion. + config PL310_ERRATA_769419 bool "PL310 errata: no automatic Store Buffer drain" depends on CACHE_L2X0 |