diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2009-03-10 10:25:03 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2009-03-10 10:25:03 +0000 |
| commit | ce67a78251af291d6aae52301b536b6bcef9a8d0 (patch) | |
| tree | 8abd5f42876e10c7500459fdd0ef92e188f76085 /arch/arm/Kconfig | |
| parent | 4930f75897bf89f8aa9e9e99dec2412bf3624d37 (diff) | |
Processor deadlock when a false hazard is created on Cortex-A8
This patch adds a workaround for the 458693 Cortex-A8 (r2p0)
erratum. It sets the corresponding bits in the auxiliary control
register so that the PLD instruction becomes a NOP.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eb750514c699..43a7330558e2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -709,6 +709,18 @@ config ARM_ERRATA_430973 prediction. This results in Cortex-A8 executing the new code sequence in the incorrect ARM or Thumb state. +config ARM_ERRATA_458693 + bool "Processor deadlock when a false hazard is created on Cortex-A8" + depends on CPU_V7 + default n + help + This option enables the workaround for the 458693 Cortex-A8 + (r2p0) erratum. For very specific sequences of memory + operations, it is possible for a hazard condition intended + for a cache line to instead be incorrectly associated with a + different cache line. This false hazard might then cause a + processor deadlock. + endmenu source "arch/arm/common/Kconfig" |