diff options
| author | Alexis Ballier <aballier@gentoo.org> | 2015-08-14 02:27:33 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene@kernel.org> | 2015-08-14 02:30:58 +0900 |
| commit | c8b34e36ca1a3e4c8ada87acefbb25119ee89347 (patch) | |
| tree | f4b7d3a3e9ef7bf0135b493cd48e5f8928201212 /arch/arm/boot/dts/exynos4412-odroidu3.dts | |
| parent | e0b12512b40c7a1cc0825773d118ecfdb464be41 (diff) | |
ARM: dts: enable SPI1 for exynos4412-odroidu3
SPI1 is available on IO Port #2 (as depicted on their website)
in PCB Revision 0.5 of Hardkernel Odroid U3 board.
The shield connects a 256KiB spi-nor flash on that bus.
Signed-off-by: Alexis Ballier <aballier@gentoo.org>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos4412-odroidu3.dts')
| -rw-r--r-- | arch/arm/boot/dts/exynos4412-odroidu3.dts | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 44684e57ead1..8632f35c6c26 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -13,6 +13,7 @@ /dts-v1/; #include "exynos4412-odroid-common.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Hardkernel ODROID-U3 board based on Exynos4412"; @@ -61,3 +62,10 @@ "Speakers", "SPKL", "Speakers", "SPKR"; }; + +&spi_1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; |