diff options
author | Shawn Guo <shawn.guo@freescale.com> | 2014-06-15 20:36:50 +0800 |
---|---|---|
committer | Nitin Garg <nitin.garg@freescale.com> | 2015-01-15 21:16:27 -0600 |
commit | 89e09713ab21098d3432e9cf37dc9bcc0a79282f (patch) | |
tree | 9fb2b00ae58a24ee8f81f95ac11a4adce1a658f2 /arch/arm/boot/dts/imx6dl.dtsi | |
parent | 03337e01f89729949a475e2b1f016b012db8b0d7 (diff) |
ARM: dts: imx6qdl: use DT macro for clock ID
Switch to use DT macro for clock ID, so that device tree source is more
readable.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick from community IMX tree]
Conflicts:
arch/arm/boot/dts/imx6dl.dtsi
arch/arm/boot/dts/imx6qdl.dtsi
Diffstat (limited to 'arch/arm/boot/dts/imx6dl.dtsi')
-rw-r--r-- | arch/arm/boot/dts/imx6dl.dtsi | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index cbcf4b576d3c..edb7414c7e38 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -35,8 +35,11 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks 104>, <&clks 6>, <&clks 16>, - <&clks 17>, <&clks 170>; + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys"; arm-supply = <®_arm>; @@ -56,7 +59,7 @@ ocram: sram@00900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; - clocks = <&clks 142>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; }; aips1: aips-bus@02000000 { @@ -87,7 +90,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021f8000 0x4000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 116>; + clocks = <&clks IMX6DL_CLK_I2C4>; status = "disabled"; }; }; @@ -95,9 +98,9 @@ }; &ldb { - clocks = <&clks 33>, <&clks 34>, - <&clks 39>, <&clks 40>, - <&clks 135>, <&clks 136>; + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di0", "di1"; |