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author | Max Krummenacher <max.krummenacher@toradex.com> | 2014-09-15 15:57:05 +0200 |
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committer | Max Krummenacher <max.krummenacher@toradex.com> | 2014-09-15 15:58:32 +0200 |
commit | 388a296ac9f78fba8392c2191264f77c3fdb0ec3 (patch) | |
tree | 8d021e927994c8e6bbaef0030651da92eca9ebc4 /arch/arm/boot/dts/imx6qdl-colibri.dtsi | |
parent | 8a4f50a4658f8406ede0f21e643e21deff6b6c3e (diff) |
Colibri iMX6 dtb: enable weim interface
Enable the external memory bus, aka weim.
Define a sram at CS0 and one at CS1, each in non multiplexed mode.
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-colibri.dtsi')
-rw-r--r-- | arch/arm/boot/dts/imx6qdl-colibri.dtsi | 63 |
1 files changed, 62 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index a5829c14098d..e00827d75a47 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -359,12 +359,65 @@ >; }; }; + weim { + pinctrl_weim_cs1_1: weim_cs1grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 /* nEXT_CS1 */ + >; + }; + pinctrl_weim_cs2_1: weim_cs2grp-1 { + fsl,pins = < + MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 /* nEXT_CS2 */ + >; + }; + pinctrl_weim_sram_1: weim_sramgrp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 + /* address */ + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + }; }; /* PWM B */ &pwm1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_3>; + pinctrl-0 = <&pinctrl_pwm1_3>; status = "disabled"; }; /* PWM D */ @@ -462,3 +515,11 @@ non-removable; status = "okay"; }; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_sram_1 &pinctrl_weim_cs0_1 &pinctrl_weim_cs1_1 &pinctrl_weim_cs2_1>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; +}; |