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authorHuang Shijie <b32955@freescale.com>2013-05-28 14:20:12 +0800
committerShawn Guo <shawn.guo@linaro.org>2013-06-17 16:04:30 +0800
commit50fe0e903d42e9cccea7cb9c894137ae65893f54 (patch)
tree65d5988091caf4b1fce1ae12ee1e7e1f5d97e811 /arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
parent9feded1ed36551391979c3ba5e880fd70c68f93f (diff)
ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR
Enable the WEIM NOR for imx6q{dl}-sabreauto boards. For the pin conflict with SPI NOR, its status is set to "disabled". Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabreauto.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index a4466e6ebe33..e994011220e7 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -58,3 +58,22 @@
wp-gpios = <&gpio1 13 0>;
status = "okay";
};
+
+&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x08000000 0x08000000>;
+ status = "disabled"; /* pin conflict with SPI NOR */
+
+ nor@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x02000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+ 0x0000c000 0x1404a38e 0x00000000>;
+ };
+};