diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2014-08-04 16:38:45 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-01-15 21:17:50 -0600 |
| commit | 980254c32e6aaeca27771167a2d66a38b39ed1aa (patch) | |
| tree | 20ec8032726ec533bc084cbb9a9bc0c61bf5dfab /arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |
| parent | eb7813466eecb53842447da98a98c3132a80ba65 (diff) | |
ENGR00331085-1: ARM: dts: imx6qdl: enable sound-cs42888
Enable sound-cs42888 in sabreauto board. Enable clock route for esai
from external 24.576MHz OSC to internal ESAI clock via analog clock2
PADs on the SoC and pll4 so that ESAI can get an entirely synchronous
clock source against CS42888.
anaclk2 0 1 24576000
lvds2_in 0 1 24576000
pll4_sel 0 1 24576000
pll4_audio 0 1 24576000
pll4_post_div 0 1 24576000
pll4_audio_div 0 1 24576000
esai_sel 0 1 24576000
esai_pred 0 1 24576000
esai_podf 0 1 24576000
esai 0 1 24576000
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabreauto.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index bc8c22ee65e2..1ce4094a8f59 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -15,6 +15,14 @@ reg = <0x10000000 0x80000000>; }; + clocks { + codec_osc: anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + }; + sound-spdif { compatible = "fsl,imx-audio-spdif", "fsl,imx-sabreauto-spdif"; @@ -36,6 +44,38 @@ reset-delay-us = <1>; #reset-cells = <0>; }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + audio-codec = <&codec>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, + <&clks IMX6QDL_PLL4_BYPASS>, + <&clks IMX6QDL_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, + <&clks IMX6QDL_PLL4_BYPASS_SRC>; + assigned-clock-rates = <0>, <0>, <24576000>; }; &ecspi1 { @@ -54,6 +94,16 @@ }; }; +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai>; + assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, + <&clks IMX6QDL_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -186,6 +236,17 @@ compatible = "fsl,imx6-hdmi-i2c"; reg = <0x50>; }; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&codec_osc>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + }; }; &i2c3 { @@ -297,6 +358,21 @@ >; }; + pinctrl_esai: esaigrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 + MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 + MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 + MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 + MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 |