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authorSandor Yu <R01008@freescale.com>2014-08-28 13:51:50 +0800
committerNitin Garg <nitin.garg@freescale.com>2015-01-15 21:17:04 -0600
commit3f47bee4e65ed7cae21811ff90d3113a7b4b44c9 (patch)
treeea346924103a8edd19dca391387312b6a7ac7f9b /arch/arm/boot/dts/imx6qdl.dtsi
parent94b3758166277d115051dda2393a2b00755a03cb (diff)
ENGR00329096-02 dts: Enable dcic driver for imx6q/dl
Enable dcic driver for imx6q/dl SabreSD and SabreAI Signed-off-by: Sandor Yu <R01008@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 40fc70d4490f..60f1b4591e12 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -733,13 +733,23 @@
};
dcic1: dcic@020e4000 {
+ compatible = "fsl,imx6q-dcic";
reg = <0x020e4000 0x4000>;
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
+ clock-names = "dcic", "disp-axi";
+ gpr = <&gpr>;
+ status = "disabled";
};
dcic2: dcic@020e8000 {
+ compatible = "fsl,imx6q-dcic";
reg = <0x020e8000 0x4000>;
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
+ clock-names = "dcic", "disp-axi";
+ gpr = <&gpr>;
+ status = "disabled";
};
sdma: sdma@020ec000 {