diff options
| author | Robby Cai <robby.cai@nxp.com> | 2016-10-14 14:22:28 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2017-06-08 19:25:39 +0800 |
| commit | c03947fc33260e8493fbdad8d189340440c8a898 (patch) | |
| tree | e6b0f67c2d49e2a335924a6b9fc7308195504aaf /arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts | |
| parent | 61722053a2962edc07c56127e427ea02af5c3779 (diff) | |
MLK-13345-2 ARM: dts: csi: add parallel camera support on imx6sll lpddr3 arm board
since there's pin conflict between camera and epdc on this board,
we add a new dts file for csi/camera function.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts b/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts index 063ea3e3e77b..448c7d7cdf88 100644 --- a/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts +++ b/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts @@ -141,6 +141,16 @@ soc-supply = <&sw1c_reg>; }; +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -338,6 +348,28 @@ SPKVDD2-supply = <®_aud4v>; amic-mono; }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6SLL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 25 1>; + rst-gpios = <&gpio1 26 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; }; &gpc { @@ -373,6 +405,25 @@ >; }; + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088 + MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088 + MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088 + MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088 + MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088 + MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088 + MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088 + MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088 + MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088 + MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088 + MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088 + MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088 + MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; + pinctrl_led: ledgrp { fsl,pins = < MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 |