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authorFugang Duan <b38611@freescale.com>2015-08-31 16:22:19 +0800
committerNitin Garg <nitin.garg@nxp.com>2016-01-14 11:00:09 -0600
commit2b4837e6fb7369c9697aa5fe49c53aaeb42811dd (patch)
treee8d5de03bb51ff58588fdd0e457e6c1c42ff6899 /arch/arm/boot/dts/imx6sx-sdb.dtsi
parentc60fdafa78b281126e14e446c8559822617a026b (diff)
MLK-11460 ARM: dts: imx6sx: enet RGMII TXCLK output drive strength is weak
The current enet RGMII TXCLK rise/fall time which could be observed(~0.85ns) is longer than requirement (<=0.75ns). The current setting, SPEED/DSE/SRE=10/110/1 is used, and then it needs to increase DSE to 111 "37 Ohm @ 3.3V, 21 Ohm@1.8V, 34 Ohm for DDR". After the change RGMII TXCLK match the spec requirement. Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sx-sdb.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index aa23c06f7ee4..0bfdbdeff09d 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -331,7 +331,7 @@
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
- MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
+ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1