diff options
| author | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> | 2015-01-30 12:48:50 -0600 |
|---|---|---|
| committer | Bai Ping <b51503@freescale.com> | 2015-02-11 18:46:13 +0800 |
| commit | 0806c8dfd8adc7eb4291c1fbfc45e1e029b4b523 (patch) | |
| tree | 280b6dac84920ba026983e3003744fc234607d45 /arch/arm/boot/dts/imx6sx.dtsi | |
| parent | ca821e2dda5f7aa475c232df8ef7be183a317971 (diff) | |
MLK-9961-3 arm:dts:imx6x: Change PLL1 clock management.
Add support to leave PLL1 enabled since its required whenever ARM-PODF is
changed. With this patch PLL1 is set to bypassed mode (and enabled) whenever
ARM is sourced from step_clk.
Also change imx6dl.dtsi to use #defines instead of hard-coded numbers for
busfreq clocks.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sx.dtsi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 2a05307b0333..d4d6d4586e36 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -76,9 +76,12 @@ <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; + <&clks IMX6SX_CLK_PLL1_SYS>, + <&clks IMX6SX_PLL1_BYPASS>, + <&clks IMX6SX_CLK_PLL1>, + <&clks IMX6SX_PLL1_BYPASS_SRC> ; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src"; arm-supply = <®_arm>; soc-supply = <®_soc>; }; |