diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2016-09-06 13:19:37 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | fc2e305a4281b1f8425d87b4d5c0cde98162d4a9 (patch) | |
| tree | ce308fb06d6adfc144ea21480e02212d71f7640d /arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts | |
| parent | 0b5036dadf979fb834df93e0d42c426a772f8498 (diff) | |
MLK-13188-2 dts: imx6ull: change the usdhc root clock to 396MHz
Due to the errata ERR010450 limit, this patch change the imx6ull
usdhc root clock to 132MHz in soc related dts file, remove all
the root clock setting in board dts file, after this patch,
SDR104/HS200 work at 132MHz, DDR50/DDR52 work at 33MHz.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts index 69323b663a50..934e6f6b8502 100644 --- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts @@ -12,9 +12,6 @@ pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD0>; - assigned-clock-rates = <0>, <176000000>; cd-gpios = <>; wp-gpios = <>; vmmc-supply = <>; |