diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2019-11-29 17:22:29 +0800 |
|---|---|---|
| committer | Fugang Duan <fugang.duan@nxp.com> | 2019-11-29 17:43:08 +0800 |
| commit | ff465fbf1bcee6bc2a029cdd4a96fd24583017b7 (patch) | |
| tree | 76c4ac71c69984ea4fb8f0d666013fcdaddf3263 /arch/arm/boot/dts/imx6ull.dtsi | |
| parent | 50413a667130957da1473e9bec46bb4356802963 (diff) | |
LF-257-02 dts: imx6ull: change the usdhc root clock to 396MHz
Due to the errata ERR010450 limit, this patch change the imx6ull
usdhc root clock to 132MHz in soc related dts file, remove all
the root clock setting in board dts file, after this patch,
SDR104/HS200 work at 132MHz, DDR50/DDR52 work at 33MHz.
(merged from commit: 1a3160ae69f725237752f65ee7bd47f5db4cfc1d)
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6ull.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6ull.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index db5e5f98379b..8624728256ba 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -46,10 +46,16 @@ &usdhc1 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; &usdhc2 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; / { |