diff options
| author | Sandor Yu <R01008@freescale.com> | 2015-11-17 17:20:51 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:20:42 +0300 |
| commit | 40db0b8fb31ea29166d3d9bdedd7e1f376e87be5 (patch) | |
| tree | 024994a6342f4780d0c4545b526558a7cc7a93bd /arch/arm/boot/dts/imx7d.dtsi | |
| parent | 12d30476ef8b797a0af11093a339f17a2e8cf2cb (diff) | |
MLK-11859: dts: Fix imx7D mipi csi reset bit error
There is a error in i.MX7D RM RevB.
Actually the register of SRC_MIPIPHY_RCR(src offset 0x28)
bit 1 for MIPI PHY Master Reset
bit 2 for MIPI PHY Slave Reset.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit 4f3128a79c023319c9e21690be866dc46a9d6816)
Diffstat (limited to 'arch/arm/boot/dts/imx7d.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7d.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index ed0593309472..67348ccae257 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -341,7 +341,7 @@ <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; clock-names = "mipi_clk", "phy_clk"; mipi-phy-supply = <®_1p0d>; - csis-phy-reset = <&src 0x28 1>; + csis-phy-reset = <&src 0x28 2>; bus-width = <4>; status = "disabled"; }; |