diff options
| author | Sandor Yu <R01008@freescale.com> | 2015-11-17 17:20:51 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 11:02:22 -0600 |
| commit | a798e63e95342b748fef521f81319fcc6e04101d (patch) | |
| tree | e495a2c85cfc9e0ef3939e6598ea233b903a10ee /arch/arm/boot/dts/imx7d.dtsi | |
| parent | a5c6731837d72740a3b5f000b67b3414fd0b5326 (diff) | |
MLK-11859: dts: Fix imx7D mipi csi reset bit error
There is a error in i.MX7D RM RevB.
Actually the register of SRC_MIPIPHY_RCR(src offset 0x28)
bit 1 for MIPI PHY Master Reset
bit 2 for MIPI PHY Slave Reset.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit 4f3128a79c023319c9e21690be866dc46a9d6816)
Diffstat (limited to 'arch/arm/boot/dts/imx7d.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7d.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 8033e1e9390c..4522dab175d5 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -857,7 +857,7 @@ <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; clock-names = "mipi_clk", "phy_clk"; mipi-phy-supply = <®_1p0d>; - csis-phy-reset = <&src 0x28 1>; + csis-phy-reset = <&src 0x28 2>; bus-width = <4>; status = "disabled"; }; |