diff options
| author | Octavian Purdila <octavian.purdila@nxp.com> | 2017-02-22 17:32:46 +0200 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:39 +0800 |
| commit | fc68f38a4d22b46d1986e327b846955b132de107 (patch) | |
| tree | 2a988f246c43060ed0838f416dee5f5e343beeb5 /arch/arm/boot/dts/imx7s.dtsi | |
| parent | 033a3b90391e9e1942e32fa2687c4a463528d55a (diff) | |
MLK-13869 ARM: dts: imx7: route interrupts through GPC
We need to "logically" route interrupts through GPC instead of directly
through GIC in order to support low power mode with SCU and L2 off.
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7s.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7s.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index ab7fb18dff0e..45414690fd04 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -317,6 +317,7 @@ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <8000000>; }; aips1: aips-bus@30000000 { @@ -524,6 +525,21 @@ anatop-max-voltage = <1200000>; anatop-enable-bit = <0>; }; + + reg_1p2: regulator-vdd1p2@220 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + anatop-reg-offset = <0x220>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <1100000>; + anatop-max-voltage = <1300000>; + anatop-enable-bit = <31>; + }; + }; snvs: snvs@30370000 { @@ -580,6 +596,10 @@ #interrupt-cells = <3>; interrupt-parent = <&intc>; #power-domain-cells = <1>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; + mipi-phy-supply = <®_1p0d>; + pcie-phy-supply = <®_1p0d>; + vcc-supply = <®_1p2>; pgc { #address-cells = <1>; |