diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2016-01-18 21:52:14 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 67a22ba638c84759f5cfc8f51538d697633abffc (patch) | |
| tree | 4e102150c75d6a74c87b0d5934fc2c0e32a53600 /arch/arm/boot/dts/imx7s.dtsi | |
| parent | 67f3f60c383a882b50e1997505a7a3d70f986c2c (diff) | |
MLK-12170-2 dts: imx7d: add tuning-start-tap for usdhc
MX7D uSDHC has a bit long delay line in SoC internally, pre-set a safe
tuning start point to skip first 20 meaningless cells tuning.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7s.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7s.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 417840309226..b565aa19cdb5 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -931,6 +931,7 @@ <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, <&clks IMX7D_USDHC1_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; bus-width = <4>; status = "disabled"; }; @@ -943,6 +944,7 @@ <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_USDHC2_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; bus-width = <4>; status = "disabled"; }; @@ -955,6 +957,7 @@ <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_USDHC3_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; bus-width = <4>; status = "disabled"; }; |