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authorDong Aisheng <aisheng.dong@nxp.com>2017-05-10 15:04:14 +0800
committerLeonard Crestez <leonard.crestez@nxp.com>2018-08-24 12:41:33 +0300
commit30a80e6e0f7daf3031d9708a7ff5a3146bb66092 (patch)
treede19d6a6d2e49b6d9b76fda2a6df94612beac8b5 /arch/arm/boot/dts/imx7ulp-pinfunc.h
parentbbaac9a7626ec28700ee7f4303eb4ec8b468ee95 (diff)
MLK-14866-1 dt-bindings: pinctrl: add imx7ulp binding doc
Add i.MX7ULP binding doc. Note i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux and config register as follows: <mux_conf_reg input_reg mux_mode input_val> Also fix the copyright. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp-pinfunc.h')
-rw-r--r--arch/arm/boot/dts/imx7ulp-pinfunc.h13
1 files changed, 3 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/imx7ulp-pinfunc.h b/arch/arm/boot/dts/imx7ulp-pinfunc.h
index b1b6a71f2cd1..388345d62db5 100644
--- a/arch/arm/boot/dts/imx7ulp-pinfunc.h
+++ b/arch/arm/boot/dts/imx7ulp-pinfunc.h
@@ -1,5 +1,6 @@
/*
- * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -12,15 +13,7 @@
/*
* The pin function ID is a tuple of
- * <mux_conf_reg mux2_reg mux_mode mux2_val>
- *
- * !!! IMPORTANT NOTE !!!
- *
- * There's common mux_reg & conf_reg register for each pad on ULP1 device, so the first
- * two values are defined as same value. Extra non-zero mux2_reg value within the tuple
- * means that there's additional mux2 control register that must be configured to
- * mux2_val accordingly to fetch desired pin functionality on ULP1 device.
- *
+ * <mux_conf_reg input_reg mux_mode input_val>
*/
#define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0