diff options
author | Andrew Lunn <andrew@lunn.ch> | 2014-02-22 20:14:45 +0100 |
---|---|---|
committer | Jason Cooper <jason@lakedaemon.net> | 2014-02-22 20:39:06 +0000 |
commit | e7c8f3808be854379c9784745663a55371cbf232 (patch) | |
tree | fd9240abe3eeed2d0dee446a41e5049ded7f62c3 /arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | |
parent | c3b6144acb6b684bf1e9ae413e2f09825e314c61 (diff) |
ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT
The mv88f6281gtw_ge has a ethernet switch connected to the ethernet
port of the SoC. Convert the platform device instantiation to a DT
instantiation.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: florian@openwrt.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts')
-rw-r--r-- | arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index dc86429756d7..2cb0dc529165 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -122,4 +122,66 @@ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0>; + dsa,mii-bus = <ðphy0>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0>; /* MDIO address 0, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@ff { + reg = <0xff>; /* No phy attached */ + speed = <1000>; + duplex = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; }; |