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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2012-08-13 14:39:03 +0530
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2012-09-19 13:00:37 +0530
commit3c7c5dab44d6c8861bc86dab924353d8d40344f8 (patch)
tree43925a23bdd177836d4428710c4cb8b05af7009c /arch/arm/boot/dts/omap5.dtsi
parentfa6d79d27614223d82418023b7f5300f1a1530d3 (diff)
ARM: OMAP5: Enable arch timer support
Enable Cortex A15 generic timer support for OMAP5 based SOCs. The CPU local timers run on the free running real time counter clock. Acked-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/boot/dts/omap5.dtsi')
-rw-r--r--arch/arm/boot/dts/omap5.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e527083746..7b986eddd0b9 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
cpus {
cpu@0 {
compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /* 14th PPI IRQ, active low level-sensitive */
+ interrupts = <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
};
cpu@1 {
compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /* 14th PPI IRQ, active low level-sensitive */
+ interrupts = <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
};
};