diff options
| author | Andrey Gusakov <andrey.gusakov@cogentembedded.com> | 2014-12-18 23:41:52 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2014-12-23 09:18:16 +0900 |
| commit | f6b5dd4088d082b53eb135e1d6b4b213bf5ce127 (patch) | |
| tree | e3b25ca35529db63116ec3f66180c216f3107018 /arch/arm/boot/dts/r8a7790.dtsi | |
| parent | 09ee81da85b10e0ca876977d333c8761441ecc78 (diff) | |
ARM: shmobile: r8a7790: add MLB+ clock
Add MLB+ clock to R8A7790 device tree.
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
[Sergei: rebased, renamed, added changelog]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7790.dtsi | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index ffeff98fa16e..af30c2470f85 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1149,16 +1149,17 @@ mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, - <&zs_clk>, <&zs_clk>; + clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, + <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; clock-indices = < - R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 - R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 - R8A7790_CLK_SATA0 + R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 + R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER + R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 >; clock-output-names = - "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; + "mlb", "vin3", "vin2", "vin1", "vin0", "ether", + "sata1", "sata0"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |