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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2015-01-06 00:33:25 +0300
committerSimon Horman <horms+renesas@verge.net.au>2015-02-24 06:30:53 +0900
commit41650f406cdc4a420d5c08e1b407f6420323a04b (patch)
tree7612cc24609e2ef4e06b363015b592958892c484 /arch/arm/boot/dts/r8a7790.dtsi
parent4a5fcc685a84751bbec5653e942fb3d61470a66c (diff)
ARM: shmobile: r8a7790: add CAN clocks
The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree, along with the USB_EXTAL clock from which clkp2 is derived. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi22
1 files changed, 20 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 24de994443e1..e872854b4ba9 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -838,16 +838,34 @@
clock-output-names = "audio_clk_c";
};
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ clock-output-names = "usb_extal";
+ };
+
+ /* External CAN clock */
+ can_clk: can_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ clock-output-names = "can_clk";
+ status = "disabled";
+ };
+
/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7790-cpg-clocks",
"renesas,rcar-gen2-cpg-clocks";
reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>;
+ clocks = <&extal_clk &usb_extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1",
- "z";
+ "z", "rcan";
};
/* Variable factor clocks */