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authorVipul Kumar Samar <vipulkumar.samar@st.com>2012-07-05 11:51:47 +0800
committerViresh Kumar <viresh.kumar@linaro.org>2012-11-26 15:52:53 +0530
commit7db083e0e1b70b0300eeb5945538e725c018f8e0 (patch)
treecf0adb82f4069bb585192dd4d5bf413a4014d17e /arch/arm/boot/dts/spear1340-evb.dts
parent7cef07d5cd25b1286376d1e8948f75b89d34a37e (diff)
ARM: SPEAr: DT: Update pinctrl list
This patch updates pinctrl configuration for SPEAr SoC's. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/spear1340-evb.dts')
-rw-r--r--arch/arm/boot/dts/spear1340-evb.dts35
1 files changed, 21 insertions, 14 deletions
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index 045f7123ffac..1fc558424d96 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -38,20 +38,15 @@
st,pins = "fsmc_8bit_grp";
st,function = "fsmc";
};
- kbd {
- st,pins = "keyboard_row_col_grp",
- "keyboard_col5_grp";
- st,function = "keyboard";
- };
uart0 {
- st,pins = "uart0_grp", "uart0_enh_grp";
+ st,pins = "uart0_grp";
st,function = "uart0";
};
- i2c0-pmx {
+ i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
- i2c1-pmx {
+ i2c1 {
st,pins = "i2c1_grp";
st,function = "i2c1";
};
@@ -64,14 +59,9 @@
st,function = "spdif_out";
};
ssp0 {
- st,pins = "ssp0_grp", "ssp0_cs1_grp",
- "ssp0_cs3_grp";
+ st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
st,function = "ssp0";
};
- pwm {
- st,pins = "pwm2_grp", "pwm3_grp";
- st,function = "pwm";
- };
smi-pmx {
st,pins = "smi_grp";
st,function = "smi";
@@ -84,6 +74,18 @@
st,pins = "gmii_grp", "rgmii_grp";
st,function = "gmac";
};
+ cam0 {
+ st,pins = "cam0_grp";
+ st,function = "cam0";
+ };
+ cam1 {
+ st,pins = "cam1_grp";
+ st,function = "cam1";
+ };
+ cam2 {
+ st,pins = "cam2_grp";
+ st,function = "cam2";
+ };
cam3 {
st,pins = "cam3_grp";
st,function = "cam3";
@@ -108,6 +110,11 @@
st,pins = "sata_grp";
st,function = "sata";
};
+ pcie {
+ st,pins = "pcie_grp";
+ st,function = "pcie";
+ };
+
};
};